diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp
index 167c05f9ef4..9c0c5cc5c70 100644
--- a/lib/CodeGen/MachinePipeliner.cpp
+++ b/lib/CodeGen/MachinePipeliner.cpp
@@ -2430,7 +2430,7 @@ void SwingSchedulerDAG::generateExistingPhis(
         // Use the value defined by the Phi, unless we're generating the first
         // epilog and the Phi refers to a Phi in a different stage.
         else if (VRMap[PrevStage - np].count(Def) &&
-                 (!LoopDefIsPhi || PrevStage != LastStageNum))
+                 (!LoopDefIsPhi || (PrevStage != LastStageNum) || (LoopValStage == StageScheduled)))
           PhiOp2 = VRMap[PrevStage - np][Def];
       }
 
diff --git a/test/CodeGen/PowerPC/sms-phi.ll b/test/CodeGen/PowerPC/sms-phi.ll
index 7fd59edf1c9..93975663f1b 100644
--- a/test/CodeGen/PowerPC/sms-phi.ll
+++ b/test/CodeGen/PowerPC/sms-phi.ll
@@ -8,7 +8,7 @@ define dso_local void @sha512() #0 {
 ;CHECK: epilog:
 ;CHECK:        %23:g8rc_and_g8rc_nox0 = PHI %5:g8rc_and_g8rc_nox0, %bb.3, %18:g8rc_and_g8rc_nox0, %bb.4
 ;CHECK-NEXT:   %24:g8rc = PHI %6:g8rc, %bb.3, %16:g8rc, %bb.4
-;CHECK-NEXT:   %25:g8rc = PHI %6:g8rc, %bb.3, %16:g8rc, %bb.4
+;CHECK-NEXT:   %25:g8rc = PHI %6:g8rc, %bb.3, %19:g8rc, %bb.4
   br label %1
 
 1:                                                ; preds = %1, %0