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https://github.com/RPCS3/llvm-mirror.git
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[AArch64][SVE] Spilling/filling of SVE callee-saves.
Implement the spills/fills of callee-saved SVE registers using STR and LDR instructions. Also adds the `aarch64_sve_vector_pcs` attribute to specify the callee-saved registers to be used for functions that return SVE vectors or take SVE vectors as arguments. The callee-saved registers are vector registers z8-z23 and predicate registers p4-p15. The overal frame-layout with SVE will be as follows: +-------------+ | stack args | +-------------+ | Callee Saves| | X29, X30 | |-------------| <- FP | SVE Callee | < ////////////// | saved regs | < ////////////// | z23 | < ////////////// | : | < // SCALABLE // | z8 | < ////////////// | p15 | < /// STACK //// | : | < ////////////// | p4 | < //// AREA //// +-------------+ < ////////////// | : | < ////////////// | SVE locals | < ////////////// | : | < ////////////// +-------------+ |/////////////| alignment gap. | : | | Stack objs | | : | +-------------+ <- SP after call and frame-setup Reviewers: cameron.mcinally, efriedma, greened, thegameg, ostannard, rengolin Reviewed By: ostannard Differential Revision: https://reviews.llvm.org/D68996
This commit is contained in:
Sander de Smalen
parent
6f39af85a4
commit
ca5d75ffa1
@ -594,6 +594,7 @@ lltok::Kind LLLexer::LexIdentifier() {
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KEYWORD(arm_aapcscc);
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KEYWORD(arm_aapcs_vfpcc);
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KEYWORD(aarch64_vector_pcs);
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KEYWORD(aarch64_sve_vector_pcs);
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KEYWORD(msp430_intrcc);
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KEYWORD(avr_intrcc);
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KEYWORD(avr_signalcc);
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@ -1931,6 +1931,7 @@ void LLParser::ParseOptionalDLLStorageClass(unsigned &Res) {
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/// ::= 'arm_aapcscc'
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/// ::= 'arm_aapcs_vfpcc'
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/// ::= 'aarch64_vector_pcs'
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/// ::= 'aarch64_sve_vector_pcs'
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/// ::= 'msp430_intrcc'
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/// ::= 'avr_intrcc'
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/// ::= 'avr_signalcc'
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@ -1977,6 +1978,9 @@ bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
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case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
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case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
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case lltok::kw_aarch64_vector_pcs:CC = CallingConv::AArch64_VectorCall; break;
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case lltok::kw_aarch64_sve_vector_pcs:
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CC = CallingConv::AArch64_SVE_VectorCall;
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break;
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case lltok::kw_msp430_intrcc: CC = CallingConv::MSP430_INTR; break;
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case lltok::kw_avr_intrcc: CC = CallingConv::AVR_INTR; break;
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case lltok::kw_avr_signalcc: CC = CallingConv::AVR_SIGNAL; break;
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@ -142,6 +142,7 @@ enum Kind {
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kw_arm_aapcscc,
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kw_arm_aapcs_vfpcc,
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kw_aarch64_vector_pcs,
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kw_aarch64_sve_vector_pcs,
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kw_msp430_intrcc,
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kw_avr_intrcc,
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kw_avr_signalcc,
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@ -364,6 +364,9 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
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case CallingConv::ARM_AAPCS: Out << "arm_aapcscc"; break;
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case CallingConv::ARM_AAPCS_VFP: Out << "arm_aapcs_vfpcc"; break;
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case CallingConv::AArch64_VectorCall: Out << "aarch64_vector_pcs"; break;
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case CallingConv::AArch64_SVE_VectorCall:
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Out << "aarch64_sve_vector_pcs";
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break;
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case CallingConv::MSP430_INTR: Out << "msp430_intrcc"; break;
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case CallingConv::AVR_INTR: Out << "avr_intrcc "; break;
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case CallingConv::AVR_SIGNAL: Out << "avr_signalcc "; break;
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@ -405,10 +405,10 @@ def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
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// Functions taking SVE arguments or returning an SVE type
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// must (additionally) preserve full Z8-Z23 and predicate registers P4-P15
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def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
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X25, X26, X27, X28, LR, FP,
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(sequence "Z%u", 8, 23),
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(sequence "P%u", 4, 15))>;
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def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),
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(sequence "P%u", 4, 15),
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X19, X20, X21, X22, X23, X24,
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X25, X26, X27, X28, LR, FP)>;
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// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
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// 'this' and the pointer return value are both passed in X0 in these cases,
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@ -486,5 +486,7 @@ def CSR_AArch64_RT_MostRegs_SCS
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: CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>;
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def CSR_AArch64_AAVPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>;
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def CSR_AArch64_SVE_AAPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_SVE_AAPCS, X18)>;
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def CSR_AArch64_AAPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>;
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@ -834,6 +834,20 @@ static bool isTargetDarwin(const MachineFunction &MF) {
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return MF.getSubtarget<AArch64Subtarget>().isTargetDarwin();
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}
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// Convenience function to determine whether I is an SVE callee save.
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bool IsSVECalleeSave(MachineBasicBlock::iterator I) {
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switch (I->getOpcode()) {
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default:
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return false;
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case AArch64::STR_ZXI:
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case AArch64::STR_PXI:
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case AArch64::LDR_ZXI:
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case AArch64::LDR_PXI:
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return I->getFlag(MachineInstr::FrameSetup) ||
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I->getFlag(MachineInstr::FrameDestroy);
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}
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}
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void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.begin();
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@ -965,7 +979,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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// and pre-inc if we decided to combine the callee-save and local stack
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// pointer bump above.
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MachineBasicBlock::iterator End = MBB.end();
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while (MBBI != End && MBBI->getFlag(MachineInstr::FrameSetup)) {
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while (MBBI != End && MBBI->getFlag(MachineInstr::FrameSetup) &&
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!IsSVECalleeSave(MBBI)) {
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if (CombineSPBump)
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fixupCalleeSaveRestoreStackOffset(*MBBI, AFI->getLocalStackSize(),
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NeedsWinCFI, &HasWinCFI);
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@ -1107,7 +1122,35 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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NumBytes = 0;
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}
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emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -SVEStackSize, TII,
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StackOffset AllocateBefore = SVEStackSize, AllocateAfter = {};
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MachineBasicBlock::iterator CalleeSavesBegin = MBBI, CalleeSavesEnd = MBBI;
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// Process the SVE callee-saves to determine what space needs to be
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// allocated.
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if (AFI->getSVECalleeSavedStackSize()) {
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// Find callee save instructions in frame.
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CalleeSavesBegin = MBBI;
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assert(IsSVECalleeSave(CalleeSavesBegin) && "Unexpected instruction");
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while (IsSVECalleeSave(MBBI) && MBBI != MBB.getFirstTerminator())
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++MBBI;
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CalleeSavesEnd = MBBI;
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int64_t OffsetToFirstCalleeSaveFromSP =
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MFI.getObjectOffset(AFI->getMaxSVECSFrameIndex());
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StackOffset OffsetToCalleeSavesFromSP =
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StackOffset(OffsetToFirstCalleeSaveFromSP, MVT::nxv1i8) + SVEStackSize;
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AllocateBefore -= OffsetToCalleeSavesFromSP;
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AllocateAfter = SVEStackSize - AllocateBefore;
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}
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// Allocate space for the callee saves (if any).
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emitFrameOffset(MBB, CalleeSavesBegin, DL, AArch64::SP, AArch64::SP,
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-AllocateBefore, TII,
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MachineInstr::FrameSetup);
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// Finally allocate remaining SVE stack space.
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emitFrameOffset(MBB, CalleeSavesEnd, DL, AArch64::SP, AArch64::SP,
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-AllocateAfter, TII,
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MachineInstr::FrameSetup);
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// Allocate space for the rest of the frame.
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@ -1444,7 +1487,8 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock::iterator Begin = MBB.begin();
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while (LastPopI != Begin) {
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--LastPopI;
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if (!LastPopI->getFlag(MachineInstr::FrameDestroy)) {
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if (!LastPopI->getFlag(MachineInstr::FrameDestroy) ||
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IsSVECalleeSave(LastPopI)) {
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++LastPopI;
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break;
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} else if (CombineSPBump)
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@ -1476,11 +1520,53 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
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NumBytes -= PrologueSaveSize;
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assert(NumBytes >= 0 && "Negative stack allocation size!?");
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// Process the SVE callee-saves to determine what space needs to be
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// deallocated.
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StackOffset DeallocateBefore = {}, DeallocateAfter = SVEStackSize;
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MachineBasicBlock::iterator RestoreBegin = LastPopI, RestoreEnd = LastPopI;
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if (AFI->getSVECalleeSavedStackSize()) {
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RestoreBegin = std::prev(RestoreEnd);;
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while (IsSVECalleeSave(RestoreBegin) &&
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RestoreBegin != MBB.begin())
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--RestoreBegin;
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++RestoreBegin;
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assert(IsSVECalleeSave(RestoreBegin) &&
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IsSVECalleeSave(std::prev(RestoreEnd)) && "Unexpected instruction");
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int64_t OffsetToFirstCalleeSaveFromSP =
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MFI.getObjectOffset(AFI->getMaxSVECSFrameIndex());
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StackOffset OffsetToCalleeSavesFromSP =
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StackOffset(OffsetToFirstCalleeSaveFromSP, MVT::nxv1i8) + SVEStackSize;
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DeallocateBefore = OffsetToCalleeSavesFromSP;
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DeallocateAfter = SVEStackSize - DeallocateBefore;
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}
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// Deallocate the SVE area.
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if (SVEStackSize)
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if (!AFI->isStackRealigned())
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emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, SVEStackSize,
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TII, MachineInstr::FrameDestroy);
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if (SVEStackSize) {
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if (AFI->isStackRealigned()) {
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if (AFI->getSVECalleeSavedStackSize())
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// Set SP to start of SVE area, from which the callee-save reloads
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// can be done. The code below will deallocate the stack space
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// space by moving FP -> SP.
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emitFrameOffset(MBB, RestoreBegin, DL, AArch64::SP, AArch64::FP,
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-SVEStackSize, TII, MachineInstr::FrameDestroy);
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} else {
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if (AFI->getSVECalleeSavedStackSize()) {
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// Deallocate the non-SVE locals first before we can deallocate (and
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// restore callee saves) from the SVE area.
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emitFrameOffset(MBB, RestoreBegin, DL, AArch64::SP, AArch64::SP,
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{NumBytes, MVT::i8}, TII, MachineInstr::FrameDestroy);
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NumBytes = 0;
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}
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emitFrameOffset(MBB, RestoreBegin, DL, AArch64::SP, AArch64::SP,
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DeallocateBefore, TII, MachineInstr::FrameDestroy);
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emitFrameOffset(MBB, RestoreEnd, DL, AArch64::SP, AArch64::SP,
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DeallocateAfter, TII, MachineInstr::FrameDestroy);
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}
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}
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if (!hasFP(MF)) {
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bool RedZone = canUseRedZone(MF);
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@ -1813,11 +1899,28 @@ struct RegPairInfo {
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unsigned Reg2 = AArch64::NoRegister;
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int FrameIdx;
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int Offset;
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enum RegType { GPR, FPR64, FPR128 } Type;
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enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type;
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RegPairInfo() = default;
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bool isPaired() const { return Reg2 != AArch64::NoRegister; }
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unsigned getScale() const {
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switch (Type) {
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case PPR:
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return 2;
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case GPR:
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case FPR64:
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return 8;
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case ZPR:
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case FPR128:
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return 16;
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default:
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llvm_unreachable("Unsupported type");
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}
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}
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bool isScalable() const { return Type == PPR || Type == ZPR; }
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};
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} // end anonymous namespace
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@ -1842,7 +1945,8 @@ static void computeCalleeSaveRegisterPairs(
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CC == CallingConv::PreserveMost ||
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(Count & 1) == 0) &&
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"Odd number of callee-saved regs to spill!");
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int Offset = AFI->getCalleeSavedStackSize();
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int ByteOffset = AFI->getCalleeSavedStackSize();
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int ScalableByteOffset = AFI->getSVECalleeSavedStackSize();
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// On Linux, we will have either one or zero non-paired register. On Windows
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// with CFI, we can have multiple unpaired registers in order to utilize the
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// available unwind codes. This flag assures that the alignment fixup is done
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@ -1858,6 +1962,10 @@ static void computeCalleeSaveRegisterPairs(
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RPI.Type = RegPairInfo::FPR64;
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else if (AArch64::FPR128RegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::FPR128;
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else if (AArch64::ZPRRegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::ZPR;
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else if (AArch64::PPRRegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::PPR;
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else
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llvm_unreachable("Unsupported register class.");
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@ -1880,6 +1988,9 @@ static void computeCalleeSaveRegisterPairs(
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if (AArch64::FPR128RegClass.contains(NextReg))
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RPI.Reg2 = NextReg;
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break;
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case RegPairInfo::PPR:
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case RegPairInfo::ZPR:
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break;
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}
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}
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@ -1917,23 +2028,33 @@ static void computeCalleeSaveRegisterPairs(
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RPI.FrameIdx = CSI[i].getFrameIdx();
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int Scale = RPI.Type == RegPairInfo::FPR128 ? 16 : 8;
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Offset -= RPI.isPaired() ? 2 * Scale : Scale;
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int Scale = RPI.getScale();
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if (RPI.isScalable())
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ScalableByteOffset -= Scale;
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else
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ByteOffset -= RPI.isPaired() ? 2 * Scale : Scale;
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assert(!(RPI.isScalable() && RPI.isPaired()) &&
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"Paired spill/fill instructions don't exist for SVE vectors");
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// Round up size of non-pair to pair size if we need to pad the
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// callee-save area to ensure 16-byte alignment.
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if (AFI->hasCalleeSaveStackFreeSpace() && !FixupDone &&
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RPI.Type != RegPairInfo::FPR128 && !RPI.isPaired()) {
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!RPI.isScalable() && RPI.Type != RegPairInfo::FPR128 &&
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!RPI.isPaired()) {
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FixupDone = true;
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Offset -= 8;
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assert(Offset % 16 == 0);
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ByteOffset -= 8;
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assert(ByteOffset % 16 == 0);
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assert(MFI.getObjectAlignment(RPI.FrameIdx) <= 16);
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MFI.setObjectAlignment(RPI.FrameIdx, 16);
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}
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int Offset = RPI.isScalable() ? ScalableByteOffset : ByteOffset;
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assert(Offset % Scale == 0);
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RPI.Offset = Offset / Scale;
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assert((RPI.Offset >= -64 && RPI.Offset <= 63) &&
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assert(((!RPI.isScalable() && RPI.Offset >= -64 && RPI.Offset <= 63) ||
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(RPI.isScalable() && RPI.Offset >= -256 && RPI.Offset <= 255)) &&
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"Offset out of bounds for LDP/STP immediate");
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RegPairs.push_back(RPI);
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@ -2025,6 +2146,16 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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Size = 16;
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Align = 16;
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break;
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case RegPairInfo::ZPR:
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StrOpc = AArch64::STR_ZXI;
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Size = 16;
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Align = 16;
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break;
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case RegPairInfo::PPR:
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StrOpc = AArch64::STR_PXI;
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Size = 2;
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Align = 2;
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break;
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}
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LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
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if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
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@ -2065,6 +2196,11 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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if (NeedsWinCFI)
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InsertSEH(MIB, TII, MachineInstr::FrameSetup);
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// Update the StackIDs of the SVE stack slots.
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MachineFrameInfo &MFI = MF.getFrameInfo();
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if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR)
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MFI.setStackID(RPI.FrameIdx, TargetStackID::SVEVector);
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}
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return true;
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}
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@ -2116,6 +2252,16 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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Size = 16;
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Align = 16;
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break;
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case RegPairInfo::ZPR:
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LdrOpc = AArch64::LDR_ZXI;
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Size = 16;
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Align = 16;
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break;
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case RegPairInfo::PPR:
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LdrOpc = AArch64::LDR_PXI;
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Size = 2;
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Align = 2;
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break;
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}
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LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
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if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
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@ -2150,11 +2296,19 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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if (NeedsWinCFI)
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InsertSEH(MIB, TII, MachineInstr::FrameDestroy);
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};
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if (ReverseCSRRestoreSeq)
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// SVE objects are always restored in reverse order.
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for (const RegPairInfo &RPI : reverse(RegPairs))
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if (RPI.isScalable())
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EmitMI(RPI);
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else
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if (ReverseCSRRestoreSeq) {
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for (const RegPairInfo &RPI : reverse(RegPairs))
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if (!RPI.isScalable())
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EmitMI(RPI);
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} else
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for (const RegPairInfo &RPI : RegPairs)
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if (!RPI.isScalable())
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EmitMI(RPI);
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if (NeedShadowCallStackProlog) {
|
||||
@ -2202,7 +2356,12 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
|
||||
SavedRegs.set(Reg);
|
||||
|
||||
bool RegUsed = SavedRegs.test(Reg);
|
||||
unsigned PairedReg = CSRegs[i ^ 1];
|
||||
unsigned PairedReg = AArch64::NoRegister;
|
||||
if (AArch64::GPR64RegClass.contains(Reg) ||
|
||||
AArch64::FPR64RegClass.contains(Reg) ||
|
||||
AArch64::FPR128RegClass.contains(Reg))
|
||||
PairedReg = CSRegs[i ^ 1];
|
||||
|
||||
if (!RegUsed) {
|
||||
if (AArch64::GPR64RegClass.contains(Reg) &&
|
||||
!RegInfo->isReservedReg(MF, Reg)) {
|
||||
@ -2226,10 +2385,17 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
|
||||
|
||||
// Calculates the callee saved stack size.
|
||||
unsigned CSStackSize = 0;
|
||||
unsigned SVECSStackSize = 0;
|
||||
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
||||
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
||||
for (unsigned Reg : SavedRegs.set_bits())
|
||||
CSStackSize += TRI->getRegSizeInBits(Reg, MRI) / 8;
|
||||
for (unsigned Reg : SavedRegs.set_bits()) {
|
||||
auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
|
||||
if (AArch64::PPRRegClass.contains(Reg) ||
|
||||
AArch64::ZPRRegClass.contains(Reg))
|
||||
SVECSStackSize += RegSize;
|
||||
else
|
||||
CSStackSize += RegSize;
|
||||
}
|
||||
|
||||
// Save number of saved regs, so we can easily update CSStackSize later.
|
||||
unsigned NumSavedRegs = SavedRegs.count();
|
||||
@ -2249,10 +2415,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
|
||||
dbgs() << "\n";);
|
||||
|
||||
// If any callee-saved registers are used, the frame cannot be eliminated.
|
||||
unsigned MaxAlign = getStackAlignment();
|
||||
int64_t SVEStackSize =
|
||||
alignTo(determineSVEStackSize(MFI, MaxAlign), MaxAlign);
|
||||
assert(MaxAlign <= 16 && "Cannot align scalable vectors more than 16 bytes");
|
||||
alignTo(SVECSStackSize + estimateSVEStackObjectOffsets(MFI), 16);
|
||||
bool CanEliminateFrame = (SavedRegs.count() == 0) && !SVEStackSize;
|
||||
|
||||
// The CSR spill slots have not been allocated yet, so estimateStackSize
|
||||
@ -2313,6 +2477,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
|
||||
// instructions.
|
||||
AFI->setCalleeSavedStackSize(AlignedCSStackSize);
|
||||
AFI->setCalleeSaveStackHasFreeSpace(AlignedCSStackSize != CSStackSize);
|
||||
AFI->setSVECalleeSavedStackSize(alignTo(SVECSStackSize, 16));
|
||||
}
|
||||
|
||||
bool AArch64FrameLowering::enableStackSlotScavenging(
|
||||
@ -2321,9 +2486,39 @@ bool AArch64FrameLowering::enableStackSlotScavenging(
|
||||
return AFI->hasCalleeSaveStackFreeSpace();
|
||||
}
|
||||
|
||||
int64_t AArch64FrameLowering::determineSVEStackSize(MachineFrameInfo &MFI,
|
||||
unsigned &MaxAlign) const {
|
||||
// Process all fixed stack objects.
|
||||
/// returns true if there are any SVE callee saves.
|
||||
static bool getSVECalleeSaveSlotRange(const MachineFrameInfo &MFI,
|
||||
int &Min, int &Max) {
|
||||
if (!MFI.isCalleeSavedInfoValid())
|
||||
return false;
|
||||
|
||||
Min = std::numeric_limits<int>::max();
|
||||
Max = std::numeric_limits<int>::min();
|
||||
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
|
||||
for (auto &CS : CSI) {
|
||||
if (AArch64::ZPRRegClass.contains(CS.getReg()) ||
|
||||
AArch64::PPRRegClass.contains(CS.getReg())) {
|
||||
assert((Max == std::numeric_limits<int>::min() ||
|
||||
Max + 1 == CS.getFrameIdx()) &&
|
||||
"SVE CalleeSaves are not consecutive");
|
||||
|
||||
Min = std::min(Min, CS.getFrameIdx());
|
||||
Max = std::max(Max, CS.getFrameIdx());
|
||||
}
|
||||
}
|
||||
return Min != std::numeric_limits<int>::max();
|
||||
}
|
||||
|
||||
// Process all the SVE stack objects and determine offsets for each
|
||||
// object. If AssignOffsets is true, the offsets get assigned.
|
||||
// Fills in the first and last callee-saved frame indices into
|
||||
// Min/MaxCSFrameIndex, respectively.
|
||||
// Returns the size of the stack.
|
||||
static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
|
||||
int &MinCSFrameIndex,
|
||||
int &MaxCSFrameIndex,
|
||||
bool AssignOffsets) {
|
||||
// First process all fixed stack objects.
|
||||
int64_t Offset = 0;
|
||||
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
|
||||
if (MFI.getStackID(I) == TargetStackID::SVEVector) {
|
||||
@ -2332,12 +2527,41 @@ int64_t AArch64FrameLowering::determineSVEStackSize(MachineFrameInfo &MFI,
|
||||
Offset = FixedOffset;
|
||||
}
|
||||
|
||||
// Then process all callee saved slots.
|
||||
if (getSVECalleeSaveSlotRange(MFI, MinCSFrameIndex, MaxCSFrameIndex)) {
|
||||
// Make sure to align the last callee save slot.
|
||||
MFI.setObjectAlignment(MaxCSFrameIndex, 16U);
|
||||
|
||||
// Assign offsets to the callee save slots.
|
||||
for (int I = MinCSFrameIndex; I <= MaxCSFrameIndex; ++I) {
|
||||
Offset += MFI.getObjectSize(I);
|
||||
Offset = alignTo(Offset, MFI.getObjectAlignment(I));
|
||||
if (AssignOffsets) {
|
||||
LLVM_DEBUG(dbgs() << "alloc FI(" << I << ") at SP[" << Offset
|
||||
<< "]\n");
|
||||
MFI.setObjectOffset(I, -Offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Note: We don't take allocatable stack objects into
|
||||
// account yet, because allocation for those is not yet
|
||||
// implemented.
|
||||
return Offset;
|
||||
}
|
||||
|
||||
int64_t AArch64FrameLowering::estimateSVEStackObjectOffsets(
|
||||
MachineFrameInfo &MFI) const {
|
||||
int MinCSFrameIndex, MaxCSFrameIndex;
|
||||
return determineSVEStackObjectOffsets(MFI, MinCSFrameIndex, MaxCSFrameIndex, false);
|
||||
}
|
||||
|
||||
int64_t AArch64FrameLowering::assignSVEStackObjectOffsets(
|
||||
MachineFrameInfo &MFI, int &MinCSFrameIndex, int &MaxCSFrameIndex) const {
|
||||
return determineSVEStackObjectOffsets(MFI, MinCSFrameIndex, MaxCSFrameIndex,
|
||||
true);
|
||||
}
|
||||
|
||||
void AArch64FrameLowering::processFunctionBeforeFrameFinalized(
|
||||
MachineFunction &MF, RegScavenger *RS) const {
|
||||
MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
@ -2345,12 +2569,13 @@ void AArch64FrameLowering::processFunctionBeforeFrameFinalized(
|
||||
assert(getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown &&
|
||||
"Upwards growing stack unsupported");
|
||||
|
||||
unsigned MaxAlign = getStackAlignment();
|
||||
int64_t SVEStackSize = determineSVEStackSize(MFI, MaxAlign);
|
||||
int MinCSFrameIndex, MaxCSFrameIndex;
|
||||
int64_t SVEStackSize =
|
||||
assignSVEStackObjectOffsets(MFI, MinCSFrameIndex, MaxCSFrameIndex);
|
||||
|
||||
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
|
||||
AFI->setStackSizeSVE(alignTo(SVEStackSize, MaxAlign));
|
||||
assert(MaxAlign <= 16 && "Cannot align scalable vectors more than 16 bytes");
|
||||
AFI->setStackSizeSVE(alignTo(SVEStackSize, 16U));
|
||||
AFI->setMinMaxSVECSFrameIndex(MinCSFrameIndex, MaxCSFrameIndex);
|
||||
|
||||
// If this function isn't doing Win64-style C++ EH, we don't need to do
|
||||
// anything.
|
||||
|
||||
@ -101,7 +101,11 @@ public:
|
||||
private:
|
||||
bool shouldCombineCSRLocalStackBump(MachineFunction &MF,
|
||||
unsigned StackBumpBytes) const;
|
||||
int64_t determineSVEStackSize(MachineFrameInfo &MF, unsigned &MaxAlign) const;
|
||||
|
||||
int64_t estimateSVEStackObjectOffsets(MachineFrameInfo &MF) const;
|
||||
int64_t assignSVEStackObjectOffsets(MachineFrameInfo &MF,
|
||||
int &MinCSFrameIndex,
|
||||
int &MaxCSFrameIndex) const;
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
@ -3118,6 +3118,9 @@ CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
|
||||
switch (CC) {
|
||||
default:
|
||||
report_fatal_error("Unsupported calling convention.");
|
||||
case CallingConv::AArch64_SVE_VectorCall:
|
||||
// Calling SVE functions is currently not yet supported.
|
||||
report_fatal_error("Unsupported calling convention.");
|
||||
case CallingConv::WebKit_JS:
|
||||
return CC_AArch64_WebKit_JS;
|
||||
case CallingConv::GHC:
|
||||
|
||||
@ -53,8 +53,13 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
|
||||
/// Amount of stack frame size, not including callee-saved registers.
|
||||
unsigned LocalStackSize;
|
||||
|
||||
/// The start and end frame indices for the SVE callee saves.
|
||||
int MinSVECSFrameIndex;
|
||||
int MaxSVECSFrameIndex;
|
||||
|
||||
/// Amount of stack frame size used for saving callee-saved registers.
|
||||
unsigned CalleeSavedStackSize;
|
||||
unsigned SVECalleeSavedStackSize;
|
||||
bool HasCalleeSavedStackSize = false;
|
||||
|
||||
/// Number of TLS accesses using the special (combinable)
|
||||
@ -161,7 +166,6 @@ public:
|
||||
void setCalleeSaveStackHasFreeSpace(bool s) {
|
||||
CalleeSaveStackHasFreeSpace = s;
|
||||
}
|
||||
|
||||
bool isSplitCSR() const { return IsSplitCSR; }
|
||||
void setIsSplitCSR(bool s) { IsSplitCSR = s; }
|
||||
|
||||
@ -218,6 +222,22 @@ public:
|
||||
return CalleeSavedStackSize;
|
||||
}
|
||||
|
||||
// Saves the CalleeSavedStackSize for SVE vectors in 'scalable bytes'
|
||||
void setSVECalleeSavedStackSize(unsigned Size) {
|
||||
SVECalleeSavedStackSize = Size;
|
||||
}
|
||||
unsigned getSVECalleeSavedStackSize() const {
|
||||
return SVECalleeSavedStackSize;
|
||||
}
|
||||
|
||||
void setMinMaxSVECSFrameIndex(int Min, int Max) {
|
||||
MinSVECSFrameIndex = Min;
|
||||
MaxSVECSFrameIndex = Max;
|
||||
}
|
||||
|
||||
int getMinSVECSFrameIndex() const { return MinSVECSFrameIndex; }
|
||||
int getMaxSVECSFrameIndex() const { return MaxSVECSFrameIndex; }
|
||||
|
||||
void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamicTLSAccesses; }
|
||||
unsigned getNumLocalDynamicTLSAccesses() const {
|
||||
return NumLocalDynamicTLSAccesses;
|
||||
|
||||
@ -55,6 +55,8 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
|
||||
return CSR_AArch64_AllRegs_SaveList;
|
||||
if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
|
||||
return CSR_AArch64_AAVPCS_SaveList;
|
||||
if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall)
|
||||
return CSR_AArch64_SVE_AAPCS_SaveList;
|
||||
if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
|
||||
return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
|
||||
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
|
||||
@ -125,7 +127,8 @@ AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
||||
if (CC == CallingConv::AArch64_VectorCall)
|
||||
return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
|
||||
if (CC == CallingConv::AArch64_SVE_VectorCall)
|
||||
return CSR_AArch64_SVE_AAPCS_RegMask;
|
||||
return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
|
||||
: CSR_AArch64_SVE_AAPCS_RegMask;
|
||||
if (CC == CallingConv::CFGuard_Check)
|
||||
return CSR_Win_AArch64_CFGuard_Check_RegMask;
|
||||
if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
|
||||
|
||||
@ -30,6 +30,10 @@
|
||||
define void @test_address_sve_fp() nounwind { entry: unreachable }
|
||||
define void @test_stack_arg_sve() nounwind { entry: unreachable }
|
||||
define void @test_address_sve_out_of_range() nounwind { entry: unreachable }
|
||||
define aarch64_sve_vector_pcs void @save_restore_pregs_sve() nounwind { entry: unreachable }
|
||||
define aarch64_sve_vector_pcs void @save_restore_zregs_sve() nounwind { entry: unreachable }
|
||||
define aarch64_sve_vector_pcs void @save_restore_sve() nounwind { entry: unreachable }
|
||||
define aarch64_sve_vector_pcs void @save_restore_sve_realign() nounwind { entry: unreachable }
|
||||
|
||||
...
|
||||
# +----------+
|
||||
@ -328,3 +332,183 @@ body: |
|
||||
|
||||
RET_ReallyLR
|
||||
---
|
||||
...
|
||||
# CHECK-LABEL: name: save_restore_pregs_sve
|
||||
# CHECK: $sp = frame-setup ADDVL_XXI $sp, -1
|
||||
# CHECK: frame-setup STR_PXI killed $p6, $sp, 5
|
||||
# CHECK: frame-setup STR_PXI killed $p5, $sp, 6
|
||||
# CHECK: frame-setup STR_PXI killed $p4, $sp, 7
|
||||
# CHECK: $sp = frame-setup SUBXri $sp, 32, 0
|
||||
|
||||
# CHECK: $sp = frame-destroy ADDXri $sp, 32, 0
|
||||
# CHECK: $p6 = frame-destroy LDR_PXI $sp, 5
|
||||
# CHECK: $p5 = frame-destroy LDR_PXI $sp, 6
|
||||
# CHECK: $p4 = frame-destroy LDR_PXI $sp, 7
|
||||
# CHECK: $sp = frame-destroy ADDVL_XXI $sp, 1
|
||||
# CHECK: RET_ReallyLR
|
||||
name: save_restore_pregs_sve
|
||||
stack:
|
||||
- { id: 0, stack-id: default, size: 32, alignment: 16 }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
|
||||
$p4 = IMPLICIT_DEF
|
||||
$p5 = IMPLICIT_DEF
|
||||
$p6 = IMPLICIT_DEF
|
||||
|
||||
RET_ReallyLR
|
||||
---
|
||||
...
|
||||
# CHECK-LABEL: name: save_restore_zregs_sve
|
||||
# CHECK: $sp = frame-setup ADDVL_XXI $sp, -3
|
||||
# CHECK: frame-setup STR_ZXI killed $z10, $sp, 0
|
||||
# CHECK: frame-setup STR_ZXI killed $z9, $sp, 1
|
||||
# CHECK: frame-setup STR_ZXI killed $z8, $sp, 2
|
||||
# CHECK: $sp = frame-setup SUBXri $sp, 32, 0
|
||||
|
||||
# CHECK: $sp = frame-destroy ADDXri $sp, 32, 0
|
||||
# CHECK: $z10 = frame-destroy LDR_ZXI $sp, 0
|
||||
# CHECK: $z9 = frame-destroy LDR_ZXI $sp, 1
|
||||
# CHECK: $z8 = frame-destroy LDR_ZXI $sp, 2
|
||||
# CHECK: $sp = frame-destroy ADDVL_XXI $sp, 3
|
||||
# CHECK: RET_ReallyLR
|
||||
name: save_restore_zregs_sve
|
||||
stack:
|
||||
- { id: 0, stack-id: default, size: 32, alignment: 16 }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
|
||||
$z8 = IMPLICIT_DEF
|
||||
$z9 = IMPLICIT_DEF
|
||||
$z10 = IMPLICIT_DEF
|
||||
|
||||
RET_ReallyLR
|
||||
---
|
||||
...
|
||||
# Test allocation/deallocation of the stack frame together with the
|
||||
# saving/restoring of callee save registers. Fixed-stack objects
|
||||
# are allocated before the callee-saves.
|
||||
# This also adds some non-SVE callee-saves, to ensure that those are
|
||||
# paired correctly.
|
||||
#
|
||||
# CHECK-LABEL: name: save_restore_sve
|
||||
# CHECK: $sp = frame-setup STPXpre killed ${{[a-z0-9]+}}, killed $x21, $sp, -4
|
||||
# CHECK: frame-setup STPXi killed $x20, killed $x19, $sp, 2
|
||||
# CHECK: $sp = frame-setup ADDVL_XXI $sp, -19
|
||||
# CHECK: frame-setup STR_PXI killed $p15, $sp, 4
|
||||
# CHECK: frame-setup STR_PXI killed $p14, $sp, 5
|
||||
# CHECK: frame-setup STR_PXI killed $p5, $sp, 14
|
||||
# CHECK: frame-setup STR_PXI killed $p4, $sp, 15
|
||||
# CHECK: frame-setup STR_ZXI killed $z23, $sp, 2
|
||||
# CHECK: frame-setup STR_ZXI killed $z22, $sp, 3
|
||||
# CHECK: frame-setup STR_ZXI killed $z9, $sp, 16
|
||||
# CHECK: frame-setup STR_ZXI killed $z8, $sp, 17
|
||||
# CHECK: $sp = frame-setup SUBXri $sp, 32, 0
|
||||
|
||||
# CHECK: $sp = frame-destroy ADDXri $sp, 32, 0
|
||||
# CHECK: $p15 = frame-destroy LDR_PXI $sp, 4
|
||||
# CHECK: $p14 = frame-destroy LDR_PXI $sp, 5
|
||||
# CHECK: $p5 = frame-destroy LDR_PXI $sp, 14
|
||||
# CHECK: $p4 = frame-destroy LDR_PXI $sp, 15
|
||||
# CHECK: $z23 = frame-destroy LDR_ZXI $sp, 2
|
||||
# CHECK: $z22 = frame-destroy LDR_ZXI $sp, 3
|
||||
# CHECK: $z9 = frame-destroy LDR_ZXI $sp, 16
|
||||
# CHECK: $z8 = frame-destroy LDR_ZXI $sp, 17
|
||||
# CHECK: $sp = frame-destroy ADDVL_XXI $sp, 19
|
||||
# CHECK: $x20, $x19 = frame-destroy LDPXi $sp, 2
|
||||
# CHECK: $sp, ${{[a-z0-9]+}}, $x21 = frame-destroy LDPXpost $sp, 4
|
||||
# CHECK: RET_ReallyLR
|
||||
name: save_restore_sve
|
||||
fixedStack:
|
||||
- { id: 0, stack-id: sve-vec, size: 16, alignment: 16, offset: -16 }
|
||||
stack:
|
||||
- { id: 0, stack-id: default, size: 32, alignment: 16 }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
|
||||
$z8_z9_z10_z11 = IMPLICIT_DEF
|
||||
$z12_z13_z14_z15 = IMPLICIT_DEF
|
||||
$z16_z17_z18_z19 = IMPLICIT_DEF
|
||||
$z20_z21_z22_z23 = IMPLICIT_DEF
|
||||
$z24_z25_z26_z27 = IMPLICIT_DEF
|
||||
$z28_z29_z30_z31 = IMPLICIT_DEF
|
||||
$p4 = IMPLICIT_DEF
|
||||
$p5 = IMPLICIT_DEF
|
||||
$p6 = IMPLICIT_DEF
|
||||
$p7 = IMPLICIT_DEF
|
||||
$p8 = IMPLICIT_DEF
|
||||
$p9 = IMPLICIT_DEF
|
||||
$p10 = IMPLICIT_DEF
|
||||
$p11 = IMPLICIT_DEF
|
||||
$p12 = IMPLICIT_DEF
|
||||
$p13 = IMPLICIT_DEF
|
||||
$p14 = IMPLICIT_DEF
|
||||
$p15 = IMPLICIT_DEF
|
||||
|
||||
$x19 = IMPLICIT_DEF
|
||||
$x20 = IMPLICIT_DEF
|
||||
$x21 = IMPLICIT_DEF
|
||||
|
||||
RET_ReallyLR
|
||||
---
|
||||
...
|
||||
# Test allocation/deallocation of the stack frame together with the
|
||||
# saving/restoring of callee save registers. Fixed-stack objects
|
||||
# are allocated before the callee-saves.
|
||||
#
|
||||
# CHECK-LABEL: name: save_restore_sve_realign
|
||||
# CHECK: $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
|
||||
# CHECK-NEXT: $fp = frame-setup ADDXri $sp, 0, 0
|
||||
# CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -19
|
||||
# CHECK-NEXT: STR_PXI killed $p15, $sp, 4
|
||||
# CHECK-NEXT: STR_PXI killed $p14, $sp, 5
|
||||
# CHECK: STR_PXI killed $p5, $sp, 14
|
||||
# CHECK-NEXT: STR_PXI killed $p4, $sp, 15
|
||||
# CHECK-NEXT: STR_ZXI killed $z23, $sp, 2
|
||||
# CHECK-NEXT: STR_ZXI killed $z22, $sp, 3
|
||||
# CHECK: STR_ZXI killed $z9, $sp, 16
|
||||
# CHECK-NEXT: STR_ZXI killed $z8, $sp, 17
|
||||
# CHECK-NEXT: $[[TMP:x[0-9]+]] = frame-setup SUBXri $sp, 16, 0
|
||||
# CHECK-NEXT: $sp = ANDXri killed $[[TMP]]
|
||||
|
||||
# CHECK: $sp = frame-destroy ADDVL_XXI $fp, -19
|
||||
# CHECK-NEXT: $p15 = frame-destroy LDR_PXI $sp, 4
|
||||
# CHECK-NEXT: $p14 = frame-destroy LDR_PXI $sp, 5
|
||||
# CHECK: $p5 = frame-destroy LDR_PXI $sp, 14
|
||||
# CHECK-NEXT: $p4 = frame-destroy LDR_PXI $sp, 15
|
||||
# CHECK-NEXT: $z23 = frame-destroy LDR_ZXI $sp, 2
|
||||
# CHECK-NEXT: $z22 = frame-destroy LDR_ZXI $sp, 3
|
||||
# CHECK: $z9 = frame-destroy LDR_ZXI $sp, 16
|
||||
# CHECK-NEXT: $z8 = frame-destroy LDR_ZXI $sp, 17
|
||||
# CHECK-NEXT: $sp = frame-destroy ADDXri $fp, 0, 0
|
||||
# CHECK-NEXT: $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2
|
||||
# CHECK-NEXT: RET_ReallyLR
|
||||
name: save_restore_sve_realign
|
||||
fixedStack:
|
||||
- { id: 0, stack-id: sve-vec, size: 16, alignment: 16, offset: -16 }
|
||||
stack:
|
||||
- { id: 0, stack-id: default, size: 16, alignment: 32 }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
|
||||
$z8_z9_z10_z11 = IMPLICIT_DEF
|
||||
$z12_z13_z14_z15 = IMPLICIT_DEF
|
||||
$z16_z17_z18_z19 = IMPLICIT_DEF
|
||||
$z20_z21_z22_z23 = IMPLICIT_DEF
|
||||
$z24_z25_z26_z27 = IMPLICIT_DEF
|
||||
$z28_z29_z30_z31 = IMPLICIT_DEF
|
||||
$p4 = IMPLICIT_DEF
|
||||
$p5 = IMPLICIT_DEF
|
||||
$p6 = IMPLICIT_DEF
|
||||
$p7 = IMPLICIT_DEF
|
||||
$p8 = IMPLICIT_DEF
|
||||
$p9 = IMPLICIT_DEF
|
||||
$p10 = IMPLICIT_DEF
|
||||
$p11 = IMPLICIT_DEF
|
||||
$p12 = IMPLICIT_DEF
|
||||
$p13 = IMPLICIT_DEF
|
||||
$p14 = IMPLICIT_DEF
|
||||
$p15 = IMPLICIT_DEF
|
||||
|
||||
RET_ReallyLR
|
||||
---
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user