From ca727da69576a4a394b690d95fe9bf04b84e7428 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 19 Mar 2021 20:39:48 -0700 Subject: [PATCH] [RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg. Previously only immediate shifts were in WriteShift. Register shifts were grouped with IALU. Seems likely that immediate shifts would be as fast or faster than register shifts. And that immediate shifts wouldn't be any faster than IALU. So if any deserved to be in their own group it should be register shifts not immediate shifts. Rather than try to flip them let's just add more granularity and give each kind their own class. I've used new names for both to make them unambiguous and to force any downstream implementations to be forced to put correct information in their scheduler models. Reviewed By: evandro Differential Revision: https://reviews.llvm.org/D98911 --- lib/Target/RISCV/RISCVInstrInfo.td | 16 ++++++++-------- lib/Target/RISCV/RISCVInstrInfoC.td | 14 +++++++------- lib/Target/RISCV/RISCVSchedRocket.td | 12 ++++++++---- lib/Target/RISCV/RISCVSchedSiFive7.td | 12 ++++++++---- lib/Target/RISCV/RISCVSchedule.td | 12 ++++++++---- 5 files changed, 39 insertions(+), 27 deletions(-) diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td index 0f7eb248377..d58d56b673b 100644 --- a/lib/Target/RISCV/RISCVInstrInfo.td +++ b/lib/Target/RISCV/RISCVInstrInfo.td @@ -393,7 +393,7 @@ class Shift_ri funct3, string opcodestr> : RVInstIShift, - Sched<[WriteShift, ReadShift]>; + Sched<[WriteShiftImm, ReadShiftImm]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class ALU_rr funct7, bits<3> funct3, string opcodestr> @@ -418,7 +418,7 @@ class ShiftW_ri funct3, string opcodestr> : RVInstIShiftW, - Sched<[WriteShift32, ReadShift32]>; + Sched<[WriteShiftImm32, ReadShiftImm32]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class ALUW_rr funct7, bits<3> funct3, string opcodestr> @@ -491,12 +491,12 @@ def SRAI : Shift_ri<1, 0b101, "srai">; def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; -def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; +def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>; def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def XOR : ALU_rr<0b0000000, 0b100, "xor">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; -def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; -def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; +def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>; +def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>; def OR : ALU_rr<0b0000000, 0b110, "or">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def AND : ALU_rr<0b0000000, 0b111, "and">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; @@ -578,11 +578,11 @@ def ADDW : ALUW_rr<0b0000000, 0b000, "addw">, def SUBW : ALUW_rr<0b0100000, 0b000, "subw">, Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">, - Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; + Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>; def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">, - Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; + Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>; def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">, - Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; + Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>; } // Predicates = [IsRV64] //===----------------------------------------------------------------------===// diff --git a/lib/Target/RISCV/RISCVInstrInfoC.td b/lib/Target/RISCV/RISCVInstrInfoC.td index 232b2e05f40..86f96c1529b 100644 --- a/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/lib/Target/RISCV/RISCVInstrInfoC.td @@ -435,9 +435,9 @@ def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd), } def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>, - Sched<[WriteShift, ReadShift]>; + Sched<[WriteShiftImm, ReadShiftImm]>; def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>, - Sched<[WriteShift, ReadShift]>; + Sched<[WriteShiftImm, ReadShiftImm]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm), @@ -480,7 +480,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm), "c.slli", "$rd, $imm">, - Sched<[WriteShift, ReadShift]> { + Sched<[WriteShiftImm, ReadShiftImm]> { let Constraints = "$rd = $rd_wb"; let Inst{6-2} = imm{4-0}; } @@ -653,7 +653,7 @@ def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb), def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb), (ins GPRX0:$rd, uimmlog2xlennonzero:$imm), "c.slli", "$rd, $imm">, - Sched<[WriteShift, ReadShift]> { + Sched<[WriteShiftImm, ReadShiftImm]> { let Constraints = "$rd = $rd_wb"; let Inst{6-2} = imm{4-0}; let Inst{11-7} = 0; @@ -662,7 +662,7 @@ def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb), def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd), "c.slli64", "$rd">, - Sched<[WriteShift, ReadShift]> { + Sched<[WriteShiftImm, ReadShiftImm]> { let Constraints = "$rd = $rd_wb"; let Inst{6-2} = 0; let Inst{12} = 0; @@ -671,7 +671,7 @@ def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd), def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd), "c.srli64", "$rd">, - Sched<[WriteShift, ReadShift]> { + Sched<[WriteShiftImm, ReadShiftImm]> { let Constraints = "$rd = $rd_wb"; let Inst{6-2} = 0; let Inst{11-10} = 0; @@ -681,7 +681,7 @@ def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb), def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd), "c.srai64", "$rd">, - Sched<[WriteShift, ReadShift]> { + Sched<[WriteShiftImm, ReadShiftImm]> { let Constraints = "$rd = $rd_wb"; let Inst{6-2} = 0; let Inst{11-10} = 1; diff --git a/lib/Target/RISCV/RISCVSchedRocket.td b/lib/Target/RISCV/RISCVSchedRocket.td index de2cdf512e8..68e5dba94a0 100644 --- a/lib/Target/RISCV/RISCVSchedRocket.td +++ b/lib/Target/RISCV/RISCVSchedRocket.td @@ -52,8 +52,10 @@ def : WriteRes; // Integer arithmetic and logic def : WriteRes; def : WriteRes; -def : WriteRes; -def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; // Integer multiplication let Latency = 4 in { @@ -181,8 +183,10 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; diff --git a/lib/Target/RISCV/RISCVSchedSiFive7.td b/lib/Target/RISCV/RISCVSchedSiFive7.td index e57ba4f61b9..5e3b731b977 100644 --- a/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -45,8 +45,10 @@ def : WriteRes; let Latency = 3 in { def : WriteRes; def : WriteRes; -def : WriteRes; -def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; } // Integer multiplication @@ -170,8 +172,10 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; diff --git a/lib/Target/RISCV/RISCVSchedule.td b/lib/Target/RISCV/RISCVSchedule.td index 0806be8a8d8..0af4d49f5cf 100644 --- a/lib/Target/RISCV/RISCVSchedule.td +++ b/lib/Target/RISCV/RISCVSchedule.td @@ -9,8 +9,10 @@ /// Define scheduler resources associated with def operands. def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I -def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix -def WriteShift : SchedWrite; // 32 or 64-bit shift operations +def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations +def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix +def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations +def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply @@ -97,8 +99,10 @@ def ReadFMemBase : SchedRead; def ReadStoreData : SchedRead; def ReadIALU : SchedRead; def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I -def ReadShift : SchedRead; -def ReadShift32 : SchedRead; // 32-bit shift operations on RV64Ix +def ReadShiftImm : SchedRead; +def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix +def ReadShiftReg : SchedRead; +def ReadShiftReg32 : SchedRead; // 32-bit shift by register operations on RV64Ix def ReadIDiv : SchedRead; def ReadIDiv32 : SchedRead; def ReadIMul : SchedRead;