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AMDGPU/GlobalISel: Tolerate negated control flow intrinsic outputs
If the condition output is negated, swap the branch targets. This is similar to what SelectionDAG does for when SelectionDAGBuilder decides to invert the condition and swap the branches. This is leaving behind a dead constant def for some reason.
This commit is contained in:
Matt Arsenault
parent
0ce967f763
commit
cacc0ebf96
@ -2625,23 +2625,42 @@ bool AMDGPULegalizerInfo::legalizeBuildVector(
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return true;
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}
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// Check that this is a G_XOR x, -1
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static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI) {
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if (MI.getOpcode() != TargetOpcode::G_XOR)
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return false;
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auto ConstVal = getConstantVRegVal(MI.getOperand(2).getReg(), MRI);
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return ConstVal && *ConstVal == -1;
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}
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// Return the use branch instruction, otherwise null if the usage is invalid.
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static MachineInstr *verifyCFIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineInstr *&Br,
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MachineBasicBlock *&UncondBrTarget) {
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static MachineInstr *
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verifyCFIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr *&Br,
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MachineBasicBlock *&UncondBrTarget, bool &Negated) {
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Register CondDef = MI.getOperand(0).getReg();
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if (!MRI.hasOneNonDBGUse(CondDef))
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return nullptr;
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MachineBasicBlock *Parent = MI.getParent();
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MachineInstr &UseMI = *MRI.use_instr_nodbg_begin(CondDef);
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if (UseMI.getParent() != Parent ||
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UseMI.getOpcode() != AMDGPU::G_BRCOND)
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MachineInstr *UseMI = &*MRI.use_instr_nodbg_begin(CondDef);
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if (isNot(MRI, *UseMI)) {
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Register NegatedCond = UseMI->getOperand(0).getReg();
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if (!MRI.hasOneNonDBGUse(NegatedCond))
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return nullptr;
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// We're deleting the def of this value, so we need to remove it.
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UseMI->eraseFromParent();
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UseMI = &*MRI.use_instr_nodbg_begin(NegatedCond);
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Negated = true;
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}
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if (UseMI->getParent() != Parent || UseMI->getOpcode() != AMDGPU::G_BRCOND)
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return nullptr;
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// Make sure the cond br is followed by a G_BR, or is the last instruction.
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MachineBasicBlock::iterator Next = std::next(UseMI.getIterator());
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MachineBasicBlock::iterator Next = std::next(UseMI->getIterator());
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if (Next == Parent->end()) {
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MachineFunction::iterator NextMBB = std::next(Parent->getIterator());
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if (NextMBB == Parent->getParent()->end()) // Illegal intrinsic use.
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@ -2654,7 +2673,7 @@ static MachineInstr *verifyCFIntrinsic(MachineInstr &MI,
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UncondBrTarget = Br->getOperand(0).getMBB();
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}
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return &UseMI;
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return UseMI;
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}
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bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
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@ -4467,7 +4486,9 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
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case Intrinsic::amdgcn_else: {
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MachineInstr *Br = nullptr;
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MachineBasicBlock *UncondBrTarget = nullptr;
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if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI, Br, UncondBrTarget)) {
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bool Negated = false;
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if (MachineInstr *BrCond =
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verifyCFIntrinsic(MI, MRI, Br, UncondBrTarget, Negated)) {
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const SIRegisterInfo *TRI
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= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
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@ -4475,6 +4496,10 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
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Register Use = MI.getOperand(3).getReg();
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MachineBasicBlock *CondBrTarget = BrCond->getOperand(1).getMBB();
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if (Negated)
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std::swap(CondBrTarget, UncondBrTarget);
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B.setInsertPt(B.getMBB(), BrCond->getIterator());
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if (IntrID == Intrinsic::amdgcn_if) {
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B.buildInstr(AMDGPU::SI_IF)
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@ -4510,13 +4535,18 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
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case Intrinsic::amdgcn_loop: {
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MachineInstr *Br = nullptr;
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MachineBasicBlock *UncondBrTarget = nullptr;
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if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI, Br, UncondBrTarget)) {
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bool Negated = false;
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if (MachineInstr *BrCond =
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verifyCFIntrinsic(MI, MRI, Br, UncondBrTarget, Negated)) {
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const SIRegisterInfo *TRI
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= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
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MachineBasicBlock *CondBrTarget = BrCond->getOperand(1).getMBB();
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Register Reg = MI.getOperand(2).getReg();
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if (Negated)
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std::swap(CondBrTarget, UncondBrTarget);
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B.setInsertPt(B.getMBB(), BrCond->getIterator());
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B.buildInstr(AMDGPU::SI_LOOP)
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.addUse(Reg)
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@ -5,7 +5,9 @@
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# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_condition)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_xor_0)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_or_neg1)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_negated_multi_use)
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---
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@ -55,10 +57,63 @@ body: |
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...
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# Make sure we only match G_XOR (if), -1
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---
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name: si_if_not_condition
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name: brcond_si_if_xor_0
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 false
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%6:_(s1) = G_XOR %3, %5
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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# Make sure we only match G_XOR (if), -1
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---
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name: brcond_si_if_or_neg1
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_OR %3, %5
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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---
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name: brcond_si_if_negated_multi_use
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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@ -66,8 +121,16 @@ body: |
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_XOR %3, %5
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G_BRCOND %6, %bb.1
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S_NOP 0, implicit %6
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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@ -406,3 +406,216 @@ body: |
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bb.2:
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S_NOP 0
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...
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---
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name: brcond_si_if_negated
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body: |
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; WAVE64-LABEL: name: brcond_si_if_negated
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE64: G_BR %bb.1
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; WAVE64: bb.1:
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; WAVE64: successors: %bb.2(0x80000000)
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; WAVE64: S_NOP 0
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; WAVE64: bb.2:
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; WAVE64: S_NOP 1
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; WAVE32-LABEL: name: brcond_si_if_negated
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE32: G_BR %bb.1
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; WAVE32: bb.1:
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; WAVE32: successors: %bb.2(0x80000000)
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; WAVE32: S_NOP 0
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; WAVE32: bb.2:
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; WAVE32: S_NOP 1
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_XOR %3, %5
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G_BRCOND %6, %bb.2
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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...
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---
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name: brcond_si_if_br_negated
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body: |
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; WAVE64-LABEL: name: brcond_si_if_br_negated
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE64: G_BR %bb.3
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; WAVE64: bb.1:
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; WAVE64: successors: %bb.2(0x80000000)
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; WAVE64: S_NOP 0
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; WAVE64: bb.2:
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; WAVE64: successors: %bb.3(0x80000000)
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; WAVE64: S_NOP 1
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; WAVE64: bb.3:
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; WAVE64: S_NOP 2
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; WAVE32-LABEL: name: brcond_si_if_br_negated
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE32: G_BR %bb.3
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; WAVE32: bb.1:
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; WAVE32: successors: %bb.2(0x80000000)
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; WAVE32: S_NOP 0
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; WAVE32: bb.2:
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; WAVE32: successors: %bb.3(0x80000000)
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; WAVE32: S_NOP 1
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; WAVE32: bb.3:
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; WAVE32: S_NOP 2
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_XOR %3, %5
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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---
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name: brcond_si_loop_brcond_negated
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tracksRegLiveness: true
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body: |
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; WAVE64-LABEL: name: brcond_si_loop_brcond_negated
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
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; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
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; WAVE64: bb.1:
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; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; WAVE64: S_NOP 0
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; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; WAVE64: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE64: G_BR %bb.2
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; WAVE64: bb.2:
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; WAVE64: S_NOP 0
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; WAVE32-LABEL: name: brcond_si_loop_brcond_negated
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
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; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
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; WAVE32: bb.1:
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; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; WAVE32: S_NOP 0
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; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; WAVE32: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE32: G_BR %bb.2
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; WAVE32: bb.2:
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; WAVE32: S_NOP 0
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s64) = COPY $sgpr0_sgpr1
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bb.1:
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successors: %bb.1, %bb.2
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S_NOP 0
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%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
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%4:_(s1) = G_CONSTANT i1 true
|
||||
%5:_(s1) = G_XOR %3, %4
|
||||
G_BRCOND %5, %bb.1
|
||||
|
||||
bb.2:
|
||||
S_NOP 0
|
||||
...
|
||||
|
||||
---
|
||||
name: brcond_si_loop_brcond_br_negated
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; WAVE64-LABEL: name: brcond_si_loop_brcond_br_negated
|
||||
; WAVE64: bb.0:
|
||||
; WAVE64: successors: %bb.1(0x80000000)
|
||||
; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
|
||||
; WAVE64: bb.1:
|
||||
; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; WAVE64: S_NOP 0
|
||||
; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
|
||||
; WAVE64: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; WAVE64: G_BR %bb.1
|
||||
; WAVE64: bb.2:
|
||||
; WAVE64: S_NOP 0
|
||||
; WAVE32-LABEL: name: brcond_si_loop_brcond_br_negated
|
||||
; WAVE32: bb.0:
|
||||
; WAVE32: successors: %bb.1(0x80000000)
|
||||
; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
|
||||
; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
|
||||
; WAVE32: bb.1:
|
||||
; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; WAVE32: S_NOP 0
|
||||
; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
|
||||
; WAVE32: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; WAVE32: G_BR %bb.1
|
||||
; WAVE32: bb.2:
|
||||
; WAVE32: S_NOP 0
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s64) = COPY $sgpr0_sgpr1
|
||||
|
||||
bb.1:
|
||||
successors: %bb.1, %bb.2
|
||||
S_NOP 0
|
||||
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
|
||||
%4:_(s1) = G_CONSTANT i1 true
|
||||
%5:_(s1) = G_XOR %3, %4
|
||||
G_BRCOND %5, %bb.2
|
||||
G_BR %bb.1
|
||||
|
||||
bb.2:
|
||||
S_NOP 0
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user