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[X86] Autogenerate complete checks. NFC

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llvm-svn: 346188
This commit is contained in:
Craig Topper 2018-11-06 00:31:27 +00:00
parent dce8965a9a
commit cad75e30da
6 changed files with 74 additions and 35 deletions
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35
test/CodeGen/X86/2009-06-05-VZextByteShort.ll
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@ -1,9 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=core2 | FileCheck %s
define <4 x i16> @a(i32* %x1) nounwind {
; CHECK-LABEL: a:
; CHECK: shrl %[[R:[^,]+]]
; CHECK-NEXT: movd %[[R]], %xmm0
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: retl
%x2 = load i32, i32* %x1
@ -15,9 +19,12 @@ define <4 x i16> @a(i32* %x1) nounwind {
define <8 x i16> @b(i32* %x1) nounwind {
; CHECK-LABEL: b:
; CHECK: shrl %e[[R:.]]x
; CHECK-NEXT: movzwl %[[R]]x, %e[[R]]x
; CHECK-NEXT: movd %e[[R]]x, %xmm0
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: retl
%x2 = load i32, i32* %x1
@ -29,9 +36,12 @@ define <8 x i16> @b(i32* %x1) nounwind {
define <8 x i8> @c(i32* %x1) nounwind {
; CHECK-LABEL: c:
; CHECK: shrl %e[[R:.]]x
; CHECK-NEXT: movzwl %[[R]]x, %e[[R]]x
; CHECK-NEXT: movd %e[[R]]x, %xmm0
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: retl
%x2 = load i32, i32* %x1
@ -43,9 +53,12 @@ define <8 x i8> @c(i32* %x1) nounwind {
define <16 x i8> @d(i32* %x1) nounwind {
; CHECK-LABEL: d:
; CHECK: shrl %e[[R:.]]x
; CHECK-NEXT: movzbl %[[R]]l, %e[[R]]x
; CHECK-NEXT: movd %e[[R]]x, %xmm0
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: retl
%x2 = load i32, i32* %x1

23
test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=corei7 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i8:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
@ -13,15 +14,29 @@ target triple = "x86_64-unknown-linux-gnu"
; Also make sure that we sign-extend it.
; Based on /gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c
; CHECK: main
define i32 @main() nounwind uwtable {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmovsxbq {{.*}}(%rip), %xmm0
; CHECK-NEXT: pmovsxbq {{.*}}(%rip), %xmm1
; CHECK-NEXT: pextrq $1, %xmm1, %rax
; CHECK-NEXT: pextrq $1, %xmm0, %rcx
; CHECK-NEXT: cqto
; CHECK-NEXT: idivq %rcx
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: movq %xmm1, %rax
; CHECK-NEXT: movq %xmm0, %rcx
; CHECK-NEXT: cqto
; CHECK-NEXT: idivq %rcx
; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; CHECK-NEXT: pextrw $0, %xmm0, {{.*}}(%rip)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
entry:
; CHECK: pmovsxbq i(%rip), %
; CHECK: pmovsxbq j(%rip), %
%0 = load <2 x i8>, <2 x i8>* @i, align 8
%1 = load <2 x i8>, <2 x i8>* @j, align 8
%div = sdiv <2 x i8> %1, %0
store <2 x i8> %div, <2 x i8>* getelementptr inbounds (%union.anon, %union.anon* @res, i32 0, i32 0), align 8
ret i32 0
; CHECK: ret
}

8
test/CodeGen/X86/2012-03-15-build_vector_wl.ll
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@ -1,10 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; CHECK: build_vector_again
define <4 x i8> @build_vector_again(<16 x i8> %in) nounwind readnone {
; CHECK-LABEL: build_vector_again:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK-NEXT: retq
entry:
%out = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK: pmovzxbd
ret <4 x i8> %out
; CHECK: ret
}

11
test/CodeGen/X86/4char-promote.ll
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@ -1,14 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; A test for checking PR 9623
; RUN: llc -mcpu=corei7 < %s | FileCheck %s
target triple = "x86_64-apple-darwin"
; CHECK: pmulld
; CHECK: paddd
; CHECK-NOT: movdqa
; CHECK: ret
define <4 x i8> @foo(<4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pmulld %xmm0, %xmm1
; CHECK-NEXT: paddd %xmm1, %xmm0
; CHECK-NEXT: retq
entry:
%binop = mul <4 x i8> %x, %y
%binop6 = add <4 x i8> %binop, %x

18
test/CodeGen/X86/avx-fp2int.ll
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@ -1,19 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
; CHECK-LABEL: test1:
; CHECK: vcvttpd2dq
; CHECK: ret
; CHECK-LABEL: test2:
; CHECK: vcvttpd2dq
; CHECK: ret
define <4 x i8> @test1(<4 x double> %d) {
; CHECK-LABEL: test1:
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
%c = fptoui <4 x double> %d to <4 x i8>
ret <4 x i8> %c
}
define <4 x i8> @test2(<4 x double> %d) {
; CHECK-LABEL: test2:
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl
%c = fptosi <4 x double> %d to <4 x i8>
ret <4 x i8> %c
}

14
test/CodeGen/X86/extract-concat.ll
View File

@ -1,6 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define void @foo(<4 x float> %in, <4 x i8>* %out) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
; CHECK-NEXT: movl $255, %eax
; CHECK-NEXT: pinsrd $3, %eax, %xmm0
; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; CHECK-NEXT: movd %xmm0, (%rdi)
; CHECK-NEXT: retq
%t0 = fptosi <4 x float> %in to <4 x i32>
%t1 = trunc <4 x i32> %t0 to <4 x i16>
%t2 = shufflevector <4 x i16> %t1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@ -9,9 +18,4 @@ define void @foo(<4 x float> %in, <4 x i8>* %out) {
%t5 = insertelement <4 x i8> %t4, i8 -1, i32 3
store <4 x i8> %t5, <4 x i8>* %out
ret void
; CHECK: foo
; CHECK: cvttps2dq
; CHECK-NOT: pextrd
; CHECK: pshufb
; CHECK: ret
}