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[Hexagon] Fixing load instruction parsing and reenabling tests.

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llvm-svn: 252555
This commit is contained in:
Colin LeMahieu 2015-11-10 00:02:27 +00:00
parent 4741d0521e
commit caeaa3d918
8 changed files with 16 additions and 23 deletions
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15
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -3631,9 +3631,9 @@ let AddedComplexity = 100 in {
//===----------------------------------------------------------------------===//
let isPredicable = 1, hasSideEffects = 0 in
class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
bits<3> MajOp, Operand AddrOp, bit isAbs>
: LDInst <(outs RC:$dst), (ins AddrOp:$addr),
"$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
bits<3> MajOp>
: LDInst <(outs RC:$dst), (ins ImmOp:$addr),
"$dst = "#mnemonic# "(#$addr)",
[], "", V2LDST_tc_ld_SLOT01> {
bits<5> dst;
bits<19> addr;
@ -3658,7 +3658,7 @@ class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
bits<3> MajOp>
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1>, AddrModeRel {
: T_LoadAbsGP <mnemonic, RC, u32MustExt, MajOp>, AddrModeRel {
string ImmOpStr = !cast<string>(ImmOp);
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
@ -3676,10 +3676,11 @@ class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
// Template class for predicated load instructions with
// absolute addressing mode.
//===----------------------------------------------------------------------===//
let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6,
opExtendable = 2 in
class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
bit isPredNot, bit isPredNew>
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32MustExt:$absaddr),
!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
bits<5> dst;
@ -3753,7 +3754,7 @@ defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
let isAsmParserOnly = 1 in
class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
bits<3> MajOp>
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {
let BaseOpcode = BaseOp#_abs;
}

4
lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
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@ -60,9 +60,9 @@ void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCK,
if (Extended) {
if (HexagonMCInstrInfo::isDuplex(*MCII, *MCI)) {
MCInst *SubInst = const_cast<MCInst *>(MCI->getOperand(1).getInst());
HexagonMCInstrInfo::clampExtended(*MCII, *SubInst);
HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *SubInst);
} else {
HexagonMCInstrInfo::clampExtended(*MCII, *MCI);
HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *MCI);
}
Extended = false;
} else {

9
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
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@ -87,7 +87,8 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
return true;
}
void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, MCInst &MCI) {
void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
MCContext &Context, MCInst &MCI) {
assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
HexagonMCInstrInfo::isExtended(MCII, MCI));
MCOperand &exOp =
@ -95,10 +96,10 @@ void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, MCInst &MCI) {
// If the extended value is a constant, then use it for the extended and
// for the extender instructions, masking off the lower 6 bits and
// including the assumed bits.
if (exOp.isImm()) {
int64_t Value;
if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
int64_t Bits = exOp.getImm();
exOp.setImm((Bits & 0x3f) << Shift);
exOp.setExpr(MCConstantExpr::create((Value & 0x3f) << Shift, Context));
}
}

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
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@ -67,7 +67,7 @@ bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
HexagonMCChecker *Checker);
// Clamp off upper 26 bits of extendable operand for emission
void clampExtended(MCInstrInfo const &MCII, MCInst &MCI);
void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
// Return the extender for instruction at Index or nullptr if none
MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);

1
test/CodeGen/Hexagon/always-ext.ll
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@ -1,5 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; XFAIL: *
; Check that we don't generate an invalid packet with too many instructions
; due to a store that has a must-extend operand.

1
test/CodeGen/Hexagon/static.ll
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@ -1,5 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
; XFAIL: *
@num = external global i32
@acc = external global i32

1
test/MC/Disassembler/Hexagon/ld.txt
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@ -1,6 +1,5 @@
# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
# Hexagon Programmer's Reference Manual 11.5 LD
# XFAIL: *
# Load doubleword
0x90 0xff 0xd5 0x3a

6
test/MC/Hexagon/instructions/ld.s
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@ -1,12 +1,6 @@
# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
# Hexagon Programmer's Reference Manual 11.5 LD
# XFAIL: *
# Load doubleword
# CHECK: 90 ff d5 3a
r17:16 = memd(r21 + r31<<#3)
# CHECK: b0 c2 c0 49
r17:16 = memd(#168)
# CHECK: 02 40 00 00
# CHECK-NEXT: 10 c5 c0 49
r17:16 = memd(##168)