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https://github.com/RPCS3/llvm-mirror.git
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Move all Altivec stuff out into a new PPCInstrAltivec.td file.
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and zero vector support. llvm-svn: 27117
This commit is contained in:
Chris Lattner
parent
57064915a6
commit
cb5f9269a9
296
lib/Target/PowerPC/PPCInstrAltivec.td
Normal file
296
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -0,0 +1,296 @@
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//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Altivec extension to the PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Altivec transformation functions and pattern fragments.
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//
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// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
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def VSPLT_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N));
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}]>;
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def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N);
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}], VSPLT_get_imm>;
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def vecimm0 : PatLeaf<(build_vector), [{
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return PPC::isZeroVector(N);
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}]>;
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// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
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def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
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char Val;
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PPC::isVecSplatImm(N, 1, &Val);
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return getI32Imm(Val);
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}]>;
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def vecspltisb : PatLeaf<(build_vector), [{
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return PPC::isVecSplatImm(N, 1);
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}], VSPLTISB_get_imm>;
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// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
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def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
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char Val;
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PPC::isVecSplatImm(N, 2, &Val);
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return getI32Imm(Val);
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}]>;
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def vecspltish : PatLeaf<(build_vector), [{
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return PPC::isVecSplatImm(N, 2);
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}], VSPLTISH_get_imm>;
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// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
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def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
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char Val;
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PPC::isVecSplatImm(N, 4, &Val);
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return getI32Imm(Val);
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}]>;
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def vecspltisw : PatLeaf<(build_vector), [{
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return PPC::isVecSplatImm(N, 4);
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}], VSPLTISW_get_imm>;
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//===----------------------------------------------------------------------===//
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// Instruction Definitions.
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def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
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[(set VRRC:$rD, (v4f32 (undef)))]>;
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let isLoad = 1, PPC970_Unit = 2 in { // Loads.
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def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
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"lvebx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
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def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
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"lvehx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
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def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
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"lvewx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
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def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
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"lvx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
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}
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral,
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[]>, PPC970_Unit_LSU;
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def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral,
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[]>, PPC970_Unit_LSU;
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
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def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvebx $rS, $rA, $rB", LdStGeneral,
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[]>;
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def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvehx $rS, $rA, $rB", LdStGeneral,
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[]>;
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def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvewx $rS, $rA, $rB", LdStGeneral,
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[]>;
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def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
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"stvx $rS, $dst", LdStGeneral,
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[(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
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}
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let PPC970_Unit = 5 in { // VALU Operations.
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vmaddfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB))]>,
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Requires<[FPContractions]>;
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def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vperm $vD, $vA, $vB, $vC", VecPerm,
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[(set VRRC:$vD,
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(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddfp $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
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def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduwm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfsx $vD, $vB, $UIMM", VecFP,
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[]>;
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def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfux $vD, $vB, $UIMM", VecFP,
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[]>;
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def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vctsxs $vD, $vB, $UIMM", VecFP,
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[]>;
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def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vctuxs $vD, $vB, $UIMM", VecFP,
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[]>;
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def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
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"vexptefp $vD, $vB", VecFP,
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[]>;
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def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
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"vlogefp $vD, $vB", VecFP,
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[]>;
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def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmaxfp $vD, $vA, $vB", VecFP,
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[]>;
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def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vminfp $vD, $vA, $vB", VecFP,
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[]>;
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def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
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"vrefp $vD, $vB", VecFP,
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[]>;
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def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
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"vrfim $vD, $vB", VecFP,
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[]>;
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def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
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"vrfin $vD, $vB", VecFP,
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[]>;
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def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
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"vrfip $vD, $vB", VecFP,
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[]>;
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def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
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"vrfiz $vD, $vB", VecFP,
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[]>;
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def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
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"vrsqrtefp $vD, $vB", VecFP,
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[]>;
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def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubfp $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
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def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vor $vD, $vA, $vB", VecFP,
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[]>;
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def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vxor $vD, $vA, $vB", VecFP,
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[]>;
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def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltb $vD, $vB, $UIMM", VecPerm,
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[]>;
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def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vsplth $vD, $vB, $UIMM", VecPerm,
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[]>;
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def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltw $vD, $vB, $UIMM", VecPerm,
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[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))]>;
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def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisb $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
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def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltish $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
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def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisw $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
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// VX-Form Pseudo Instructions
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def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
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"vxor $vD, $vD, $vD", VecFP,
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[(set VRRC:$vD, (v4f32 vecimm0))]>;
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}
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//===----------------------------------------------------------------------===//
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// Additional Altivec Patterns
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//
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// Undef/Zero.
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def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
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def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
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def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
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def : Pat<(v16i8 vecimm0), (v16i8 (V_SET0))>;
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def : Pat<(v8i16 vecimm0), (v8i16 (V_SET0))>;
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def : Pat<(v4i32 vecimm0), (v4i32 (V_SET0))>;
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// Loads.
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def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
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def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
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def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
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// Stores.
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def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
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(STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
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def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
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(STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
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def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
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(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
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// Bit conversions.
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def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
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// Immediate vector formation with vsplti*.
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def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
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def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
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def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
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def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
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def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
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def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
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def : Pat<(fmul VRRC:$vA, VRRC:$vB),
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(VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
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// Fused multiply add and multiply sub for packed float. These are represented
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// separately from the real instructions above, for operations that must have
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// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
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def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
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(v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
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def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
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(v4i32 (LVEWX xoaddr:$src))>;
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@ -126,50 +126,6 @@ def imm16Shifted : PatLeaf<(imm), [{
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return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
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}], HI16>;
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// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
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def VSPLT_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N));
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}]>;
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def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N);
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}], VSPLT_get_imm>;
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def vecimm0 : PatLeaf<(build_vector), [{
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return PPC::isZeroVector(N);
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}]>;
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|
||||
// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
|
||||
def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
|
||||
char Val;
|
||||
PPC::isVecSplatImm(N, 1, &Val);
|
||||
return getI32Imm(Val);
|
||||
}]>;
|
||||
def vecspltisb : PatLeaf<(build_vector), [{
|
||||
return PPC::isVecSplatImm(N, 1);
|
||||
}], VSPLTISB_get_imm>;
|
||||
|
||||
// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
|
||||
def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
|
||||
char Val;
|
||||
PPC::isVecSplatImm(N, 2, &Val);
|
||||
return getI32Imm(Val);
|
||||
}]>;
|
||||
def vecspltish : PatLeaf<(build_vector), [{
|
||||
return PPC::isVecSplatImm(N, 2);
|
||||
}], VSPLTISH_get_imm>;
|
||||
|
||||
// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
|
||||
def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
|
||||
char Val;
|
||||
PPC::isVecSplatImm(N, 4, &Val);
|
||||
return getI32Imm(Val);
|
||||
}]>;
|
||||
def vecspltisw : PatLeaf<(build_vector), [{
|
||||
return PPC::isVecSplatImm(N, 4);
|
||||
}], VSPLTISW_get_imm>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// PowerPC Flag Definitions.
|
||||
@ -274,8 +230,6 @@ def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
|
||||
[(set F8RC:$rD, (undef))]>;
|
||||
def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
|
||||
[(set F4RC:$rD, (undef))]>;
|
||||
def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
|
||||
[(set VRRC:$rD, (v4f32 (undef)))]>;
|
||||
|
||||
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
|
||||
// scheduler into a branch sequence.
|
||||
@ -511,25 +465,8 @@ def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
|
||||
def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
|
||||
"ldx $rD, $src", LdStLD,
|
||||
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
|
||||
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
|
||||
"lvebx $vD, $src", LdStGeneral,
|
||||
[(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
|
||||
def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
|
||||
"lvehx $vD, $src", LdStGeneral,
|
||||
[(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
|
||||
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
|
||||
"lvewx $vD, $src", LdStGeneral,
|
||||
[(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
|
||||
def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
|
||||
"lvx $vD, $src", LdStGeneral,
|
||||
[(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
|
||||
}
|
||||
def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvsl $vD, $base, $rA", LdStGeneral,
|
||||
[]>, PPC970_Unit_LSU;
|
||||
def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvsl $vD, $base, $rA", LdStGeneral,
|
||||
[]>, PPC970_Unit_LSU;
|
||||
|
||||
let PPC970_Unit = 1 in { // FXU Operations.
|
||||
def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
"nand $rA, $rS, $rB", IntGeneral,
|
||||
@ -611,18 +548,6 @@ def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stdux $rS, $rA, $rB", LdStSTD,
|
||||
[]>, isPPC64;
|
||||
def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvebx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvehx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvewx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
|
||||
"stvx $rS, $dst", LdStGeneral,
|
||||
[(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
|
||||
}
|
||||
let PPC970_Unit = 1 in { // FXU Operations.
|
||||
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
|
||||
@ -1005,114 +930,6 @@ def RLDICR : MDForm_1<30, 1,
|
||||
}
|
||||
|
||||
|
||||
let PPC970_Unit = 5 in { // VALU Operations.
|
||||
// VA-Form instructions. 3-input AltiVec ops.
|
||||
def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
|
||||
"vmaddfp $vD, $vA, $vC, $vB", VecFP,
|
||||
[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
|
||||
VRRC:$vB))]>,
|
||||
Requires<[FPContractions]>;
|
||||
def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
|
||||
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
|
||||
[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
|
||||
VRRC:$vB)))]>,
|
||||
Requires<[FPContractions]>;
|
||||
|
||||
def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
|
||||
"vperm $vD, $vA, $vB, $vC", VecPerm,
|
||||
[(set VRRC:$vD,
|
||||
(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
|
||||
|
||||
|
||||
// VX-Form instructions. AltiVec arithmetic ops.
|
||||
def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vaddfp $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
|
||||
def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vadduwm $vD, $vA, $vB", VecGeneral,
|
||||
[(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
|
||||
def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vcfsx $vD, $vB, $UIMM", VecFP,
|
||||
[]>;
|
||||
def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vcfux $vD, $vB, $UIMM", VecFP,
|
||||
[]>;
|
||||
def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vctsxs $vD, $vB, $UIMM", VecFP,
|
||||
[]>;
|
||||
def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vctuxs $vD, $vB, $UIMM", VecFP,
|
||||
[]>;
|
||||
def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vexptefp $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vlogefp $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vmaxfp $vD, $vA, $vB", VecFP,
|
||||
[]>;
|
||||
def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vminfp $vD, $vA, $vB", VecFP,
|
||||
[]>;
|
||||
def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vrefp $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vrfim $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vrfin $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vrfip $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vrfiz $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
|
||||
"vrsqrtefp $vD, $vB", VecFP,
|
||||
[]>;
|
||||
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vsubfp $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
|
||||
def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vor $vD, $vA, $vB", VecFP,
|
||||
[]>;
|
||||
def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
||||
"vxor $vD, $vA, $vB", VecFP,
|
||||
[]>;
|
||||
|
||||
def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vspltb $vD, $vB, $UIMM", VecPerm,
|
||||
[]>;
|
||||
def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vsplth $vD, $vB, $UIMM", VecPerm,
|
||||
[]>;
|
||||
def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
||||
"vspltw $vD, $vB, $UIMM", VecPerm,
|
||||
[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
|
||||
VSPLT_shuffle_mask:$UIMM))]>;
|
||||
|
||||
def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
|
||||
"vspltisb $vD, $SIMM", VecPerm,
|
||||
[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
|
||||
def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
|
||||
"vspltish $vD, $SIMM", VecPerm,
|
||||
[(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
|
||||
def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
|
||||
"vspltisw $vD, $SIMM", VecPerm,
|
||||
[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
|
||||
|
||||
|
||||
// VX-Form Pseudo Instructions
|
||||
|
||||
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
|
||||
"vxor $vD, $vD, $vD", VecFP,
|
||||
[(set VRRC:$vD, (v4f32 vecimm0))]>;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// DWARF Pseudo Instructions
|
||||
//
|
||||
@ -1189,9 +1006,6 @@ def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
|
||||
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
|
||||
(ADDIS GPRC:$in, tconstpool:$g)>;
|
||||
|
||||
def : Pat<(fmul VRRC:$vA, VRRC:$vB),
|
||||
(VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
|
||||
|
||||
// Fused negative multiply subtract, alternate pattern
|
||||
def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
|
||||
(FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
|
||||
@ -1200,19 +1014,6 @@ def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
|
||||
(FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
|
||||
Requires<[FPContractions]>;
|
||||
|
||||
// Fused multiply add and multiply sub for packed float. These are represented
|
||||
// separately from the real instructions above, for operations that must have
|
||||
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
|
||||
def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
|
||||
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
||||
def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
|
||||
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
||||
|
||||
def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
|
||||
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
||||
def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
|
||||
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
||||
|
||||
// Standard shifts. These are represented separately from the real shifts above
|
||||
// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
|
||||
// amounts.
|
||||
@ -1244,43 +1045,5 @@ def : Pat<(f64 (extload iaddr:$src, f32)),
|
||||
def : Pat<(f64 (extload xaddr:$src, f32)),
|
||||
(FMRSD (LFSX xaddr:$src))>;
|
||||
|
||||
def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
|
||||
def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
|
||||
def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
|
||||
|
||||
|
||||
def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
|
||||
(v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
|
||||
|
||||
def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
|
||||
(v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
|
||||
|
||||
def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
|
||||
(STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
|
||||
def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
|
||||
(STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
|
||||
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
|
||||
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
|
||||
|
||||
def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
|
||||
(v4i32 (LVEWX xoaddr:$src))>;
|
||||
|
||||
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
|
||||
def : Pat<(v4i32 vecimm0), (v4i32 (V_SET0))>;
|
||||
|
||||
def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
|
||||
def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
|
||||
def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
|
||||
|
||||
|
||||
// bit_convert
|
||||
def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
|
||||
def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
|
||||
|
||||
// Same as above, but using a temporary. FIXME: implement temporaries :)
|
||||
/*
|
||||
def : Pattern<(xor GPRC:$in, imm:$imm),
|
||||
[(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
|
||||
(XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
|
||||
*/
|
||||
|
||||
include "PPCInstrAltivec.td"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user