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Minor optimization. sign-ext/anyext of undef is still undef.

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llvm-svn: 127598
This commit is contained in:
Evan Cheng 2011-03-14 18:15:55 +00:00
parent fbb846289a
commit cb70b9e80b
3 changed files with 23 additions and 5 deletions
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4
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2482,6 +2482,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
"Vector element count mismatch!");
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
else if (OpOpcode == ISD::UNDEF)
return getUNDEF(VT);
break;
case ISD::ZERO_EXTEND:
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@ -2512,6 +2514,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
OpOpcode == ISD::ANY_EXTEND)
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
else if (OpOpcode == ISD::UNDEF)
return getUNDEF(VT);
// (ext (trunx x)) -> x
if (OpOpcode == ISD::TRUNCATE) {

10
test/CodeGen/ARM/shifter_operand.ll
View File

@ -51,19 +51,19 @@ entry:
declare i8* @malloc(...)
define fastcc void @test4() nounwind {
define fastcc void @test4(i16 %addr) nounwind {
entry:
; A8: test4:
; A8: ldr r1, [r0, r0, lsl #2]
; A8: str r1, [r0, r0, lsl #2]
; A8: ldr r2, [r0, r1, lsl #2]
; A8: str r2, [r0, r1, lsl #2]
; A9: test4:
; A9: add r0, r0, r0, lsl #2
; A9: add r0, r0, r4, lsl #2
; A9: ldr r1, [r0]
; A9: str r1, [r0]
%0 = tail call i8* (...)* @malloc(i32 undef) nounwind
%1 = bitcast i8* %0 to i32*
%2 = sext i16 undef to i32
%2 = sext i16 %addr to i32
%3 = getelementptr inbounds i32* %1, i32 %2
%4 = load i32* %3, align 4
%5 = add nsw i32 %4, 1

14
test/CodeGen/ARM/undef-sext.ll Normal file
View File

@ -0,0 +1,14 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
; No need to sign-extend undef.
define i32 @t(i32* %a) nounwind {
entry:
; CHECK: t:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
%0 = sext i16 undef to i32
%1 = getelementptr inbounds i32* %a, i32 %0
%2 = load i32* %1, align 4
ret i32 %2
}