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[RISCV] Use SplatPat/SplatPat_simm5 to handle PseudoVMV_V_X_/PseudoVMV_V_I_ selection as well.

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This ensures that we'll match immediates consistently regardless
of whether we match them as a standalone splat or as part of
another operation.

While I was there I added complexities to the simm5/uimm5 patterns so
we didn't have to assume that the 1 on the non-immediate was lower
than what tablegen inferred.

I had to make a minor tweak to tablegen to fix one place that
didn't expect to see a ComplexPattern that wasn't a "leaf".

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96199
This commit is contained in:
Craig Topper 2021-02-08 09:48:25 -08:00
parent ee839f7374
commit cb8d88249b
2 changed files with 9 additions and 21 deletions
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27
lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
View File

@ -32,12 +32,10 @@ def riscv_trunc_vector : SDNode<"RISCVISD::TRUNCATE_VECTOR",
SDTypeProfile<1, 1, SDTypeProfile<1, 1,
[SDTCisVec<0>, SDTCisVec<1>]>>; [SDTCisVec<0>, SDTCisVec<1>]>>;
// Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants // Give explicit Complexity to prefer simm5/uimm5.
// precedence def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [splat_vector, rv32_splat_i64], [], 1>;
def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [splat_vector, rv32_splat_i64], [], 2>;
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>;
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
def RVVBaseAddr : ComplexPattern<iPTR, 1, "SelectRVVBaseAddr">; def RVVBaseAddr : ComplexPattern<iPTR, 1, "SelectRVVBaseAddr">;
@ -714,10 +712,10 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (splat_vector GPR:$rs1)), def : Pat<(vti.Vector (SplatPat GPR:$rs1)),
(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
GPR:$rs1, vti.AVL, vti.SEW)>; GPR:$rs1, vti.AVL, vti.SEW)>;
def : Pat<(vti.Vector (splat_vector simm5:$rs1)), def : Pat<(vti.Vector (SplatPat_simm5 simm5:$rs1)),
(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
simm5:$rs1, vti.AVL, vti.SEW)>; simm5:$rs1, vti.AVL, vti.SEW)>;
} }
@ -730,19 +728,6 @@ foreach mti = AllMasks in {
} }
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, IsRV32] in {
foreach vti = AllIntegerVectors in {
if !eq(vti.SEW, 64) then {
def : Pat<(vti.Vector (rv32_splat_i64 GPR:$rs1)),
(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
GPR:$rs1, vti.AVL, vti.SEW)>;
def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)),
(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
simm5:$rs1, vti.AVL, vti.SEW)>;
}
}
} // Predicates = [HasStdExtV, IsRV32]
let Predicates = [HasStdExtV, HasStdExtF] in { let Predicates = [HasStdExtV, HasStdExtF] in {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)), def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),

3
utils/TableGen/CodeGenDAGPatterns.cpp
View File

@ -3472,6 +3472,9 @@ private:
if (N->getNumChildren() != 1 || !N->getChild(0)->isLeaf()) if (N->getNumChildren() != 1 || !N->getChild(0)->isLeaf())
return false; return false;
if (N->getOperator()->isSubClassOf("ComplexPattern"))
return false;
const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
if (OpInfo.getNumResults() != 1 || OpInfo.getNumOperands() != 1) if (OpInfo.getNumResults() != 1 || OpInfo.getNumOperands() != 1)
return false; return false;