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[SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar or vector splats
Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
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@ -2566,17 +2566,18 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
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case ISD::SRA:
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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// SRA X, C -> adds C sign bits.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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Tmp += C->getZExtValue();
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if (Tmp > VTBits) Tmp = VTBits;
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if (ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1))) {
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APInt ShiftVal = C->getAPIntValue();
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ShiftVal += Tmp;
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Tmp = ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue();
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}
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return Tmp;
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case ISD::SHL:
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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if (ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1))) {
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// shl destroys sign bits.
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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if (C->getZExtValue() >= VTBits || // Bad shift.
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C->getZExtValue() >= Tmp) break; // Shifted all sign bits out.
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if (C->getAPIntValue().uge(VTBits) || // Bad shift.
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C->getAPIntValue().uge(Tmp)) break; // Shifted all sign bits out.
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return Tmp - C->getZExtValue();
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}
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break;
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@ -1007,8 +1007,6 @@ entry:
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define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {
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; SSE2-LABEL: blend_neg_logic_v4i32_2:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: psrld $31, %xmm1
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; SSE2-NEXT: pslld $31, %xmm1
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; SSE2-NEXT: psrad $31, %xmm1
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; SSE2-NEXT: pxor %xmm1, %xmm0
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; SSE2-NEXT: psubd %xmm0, %xmm1
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@ -1017,8 +1015,6 @@ define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {
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;
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; SSSE3-LABEL: blend_neg_logic_v4i32_2:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: psrld $31, %xmm1
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; SSSE3-NEXT: pslld $31, %xmm1
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; SSSE3-NEXT: psrad $31, %xmm1
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; SSSE3-NEXT: pxor %xmm1, %xmm0
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; SSSE3-NEXT: psubd %xmm0, %xmm1
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@ -1028,8 +1024,7 @@ define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {
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; SSE41-LABEL: blend_neg_logic_v4i32_2:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movdqa %xmm0, %xmm2
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; SSE41-NEXT: psrld $31, %xmm1
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; SSE41-NEXT: pslld $31, %xmm1
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; SSE41-NEXT: psrad $31, %xmm1
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; SSE41-NEXT: pxor %xmm3, %xmm3
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; SSE41-NEXT: psubd %xmm2, %xmm3
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; SSE41-NEXT: movdqa %xmm1, %xmm0
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@ -1039,8 +1034,7 @@ define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {
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;
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; AVX-LABEL: blend_neg_logic_v4i32_2:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsrld $31, %xmm1, %xmm1
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; AVX-NEXT: vpslld $31, %xmm1, %xmm1
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; AVX-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm2
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; AVX-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0
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