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https://github.com/RPCS3/llvm-mirror.git
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[AMDGPU] Match v_swap_b32
Differential Revision: https://reviews.llvm.org/D52677 llvm-svn: 345514
This commit is contained in:
Stanislav Mekhanoshin
parent
fd4a382026
commit
cbc5c41e5b
@ -516,6 +516,10 @@ public:
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return FMA;
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}
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bool hasSwap() const {
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return GFX9Insts;
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}
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TrapHandlerAbi getTrapHandlerAbi() const {
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return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
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}
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@ -212,6 +212,169 @@ static void shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) {
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}
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}
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// This is the same as MachineInstr::readsRegister/modifiesRegister except
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// it takes subregs into account.
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static bool instAccessReg(iterator_range<MachineInstr::const_mop_iterator> &&R,
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unsigned Reg, unsigned SubReg,
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const SIRegisterInfo &TRI) {
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for (const MachineOperand &MO : R) {
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if (!MO.isReg())
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
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TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
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if (TRI.regsOverlap(Reg, MO.getReg()))
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return true;
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} else if (MO.getReg() == Reg &&
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TargetRegisterInfo::isVirtualRegister(Reg)) {
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LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) &
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TRI.getSubRegIndexLaneMask(MO.getSubReg());
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if (Overlap.any())
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return true;
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}
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}
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return false;
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}
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static bool instReadsReg(const MachineInstr *MI,
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unsigned Reg, unsigned SubReg,
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const SIRegisterInfo &TRI) {
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return instAccessReg(MI->uses(), Reg, SubReg, TRI);
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}
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static bool instModifiesReg(const MachineInstr *MI,
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unsigned Reg, unsigned SubReg,
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const SIRegisterInfo &TRI) {
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return instAccessReg(MI->defs(), Reg, SubReg, TRI);
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}
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static TargetInstrInfo::RegSubRegPair
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getSubRegForIndex(unsigned Reg, unsigned Sub, unsigned I,
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const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) {
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if (TRI.getRegSizeInBits(Reg, MRI) != 32) {
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I));
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} else {
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LaneBitmask LM = TRI.getSubRegIndexLaneMask(Sub);
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Sub = TRI.getSubRegFromChannel(I + countTrailingZeros(LM.getAsInteger()));
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}
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}
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return TargetInstrInfo::RegSubRegPair(Reg, Sub);
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}
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// Match:
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// mov t, x
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// mov x, y
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// mov y, t
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//
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// =>
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//
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// mov t, x (t is potentially dead and move eliminated)
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// v_swap_b32 x, y
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//
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// Returns next valid instruction pointer if was able to create v_swap_b32.
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//
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// This shall not be done too early not to prevent possible folding which may
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// remove matched moves, and this should prefereably be done before RA to
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// release saved registers and also possibly after RA which can insert copies
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// too.
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//
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// This is really just a generic peephole that is not a canocical shrinking,
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// although requirements match the pass placement and it reduces code size too.
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static MachineInstr* matchSwap(MachineInstr &MovT, MachineRegisterInfo &MRI,
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const SIInstrInfo *TII) {
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assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
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MovT.getOpcode() == AMDGPU::COPY);
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unsigned T = MovT.getOperand(0).getReg();
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unsigned Tsub = MovT.getOperand(0).getSubReg();
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MachineOperand &Xop = MovT.getOperand(1);
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if (!Xop.isReg())
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return nullptr;
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unsigned X = Xop.getReg();
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unsigned Xsub = Xop.getSubReg();
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unsigned Size = TII->getOpSize(MovT, 0) / 4;
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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if (!TRI.isVGPR(MRI, X))
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return false;
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for (MachineOperand &YTop : MRI.use_nodbg_operands(T)) {
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if (YTop.getSubReg() != Tsub)
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continue;
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MachineInstr &MovY = *YTop.getParent();
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if ((MovY.getOpcode() != AMDGPU::V_MOV_B32_e32 &&
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MovY.getOpcode() != AMDGPU::COPY) ||
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MovY.getOperand(1).getSubReg() != Tsub)
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continue;
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unsigned Y = MovY.getOperand(0).getReg();
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unsigned Ysub = MovY.getOperand(0).getSubReg();
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if (!TRI.isVGPR(MRI, Y) || MovT.getParent() != MovY.getParent())
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continue;
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MachineInstr *MovX = nullptr;
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auto I = std::next(MovT.getIterator()), E = MovT.getParent()->instr_end();
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for (auto IY = MovY.getIterator(); I != E && I != IY; ++I) {
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if (instReadsReg(&*I, X, Xsub, TRI) ||
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instModifiesReg(&*I, Y, Ysub, TRI) ||
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instModifiesReg(&*I, T, Tsub, TRI) ||
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(MovX && instModifiesReg(&*I, X, Xsub, TRI))) {
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MovX = nullptr;
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break;
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}
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if (!instReadsReg(&*I, Y, Ysub, TRI)) {
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if (!MovX && instModifiesReg(&*I, X, Xsub, TRI)) {
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MovX = nullptr;
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break;
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}
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continue;
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}
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if (MovX ||
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(I->getOpcode() != AMDGPU::V_MOV_B32_e32 &&
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I->getOpcode() != AMDGPU::COPY) ||
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I->getOperand(0).getReg() != X ||
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I->getOperand(0).getSubReg() != Xsub) {
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MovX = nullptr;
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break;
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}
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MovX = &*I;
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}
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if (!MovX || I == E)
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continue;
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LLVM_DEBUG(dbgs() << "Matched v_swap_b32:\n" << MovT << *MovX << MovY);
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for (unsigned I = 0; I < Size; ++I) {
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TargetInstrInfo::RegSubRegPair X1, Y1;
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X1 = getSubRegForIndex(X, Xsub, I, TRI, MRI);
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Y1 = getSubRegForIndex(Y, Ysub, I, TRI, MRI);
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BuildMI(*MovT.getParent(), MovX->getIterator(), MovT.getDebugLoc(),
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TII->get(AMDGPU::V_SWAP_B32))
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.addDef(X1.Reg, 0, X1.SubReg)
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.addDef(Y1.Reg, 0, Y1.SubReg)
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.addReg(Y1.Reg, 0, Y1.SubReg)
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.addReg(X1.Reg, 0, X1.SubReg).getInstr();
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}
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MovX->eraseFromParent();
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MovY.eraseFromParent();
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MachineInstr *Next = &*std::next(MovT.getIterator());
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if (MRI.use_nodbg_empty(T))
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MovT.eraseFromParent();
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else
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Xop.setIsKill(false);
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return Next;
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}
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return nullptr;
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}
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bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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@ -252,6 +415,14 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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if (ST.hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
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MI.getOpcode() == AMDGPU::COPY)) {
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if (auto *NextMI = matchSwap(MI, MRI, TII)) {
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Next = NextMI->getIterator();
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continue;
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}
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}
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// Combine adjacent s_nops to use the immediate operand encoding how long
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// to wait.
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//
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564
test/CodeGen/AMDGPU/v_swap_b32.mir
Normal file
564
test/CodeGen/AMDGPU/v_swap_b32.mir
Normal file
@ -0,0 +1,564 @@
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: swap_phys_condensed
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# GCN: bb.0:
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# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
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# GCN-NEXT: S_SETPC_B64_return
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---
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name: swap_phys_condensed
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
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...
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# GCN-LABEL: name: swap_phys_sparse
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# GCN: bb.0:
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# GCN-NEXT: $vgpr3 = V_MOV_B32_e32 killed $vgpr4, implicit $exec
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# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
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# GCN-NEXT: $vgpr5 = V_MOV_B32_e32 killed $vgpr6, implicit $exec
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# GCN-NEXT: S_SETPC_B64_return
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---
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name: swap_phys_sparse
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
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$vgpr3 = V_MOV_B32_e32 killed $vgpr4, implicit $exec
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$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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$vgpr5 = V_MOV_B32_e32 killed $vgpr6, implicit $exec
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$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
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...
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# GCN-LABEL: name: swap_phys_liveout
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# GCN: bb.0:
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# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
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# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
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# GCN-NEXT: S_SETPC_B64_return
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---
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name: swap_phys_liveout
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr2, implicit $vgpr1
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...
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# GCN-LABEL: name: swap_phys_b64
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# GCN: bb.0:
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# GCN-NEXT: $vgpr0, $vgpr2 = V_SWAP_B32 $vgpr2, $vgpr0, implicit $exec
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# GCN-NEXT: $vgpr1, $vgpr3 = V_SWAP_B32 $vgpr3, $vgpr1, implicit $exec
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---
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name: swap_phys_b64
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body: |
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bb.0:
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$vgpr4_vgpr5 = COPY killed $vgpr0_vgpr1
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$vgpr0_vgpr1 = COPY killed $vgpr2_vgpr3
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$vgpr2_vgpr3 = COPY killed $vgpr4_vgpr5
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...
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# GCN-LABEL: name: swap_phys_overlap_x
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# GCN: bb.0:
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# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
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# GCN-NEXT: $vgpr3_vgpr4 = V_ADD_F64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $exec
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# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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---
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name: swap_phys_overlap_x
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body: |
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bb.0:
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$vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
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$vgpr3_vgpr4 = V_ADD_F64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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...
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# GCN-LABEL: name: swap_phys_clobber_y
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# GCN: bb.0:
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# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
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# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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---
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name: swap_phys_clobber_y
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body: |
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bb.0:
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$vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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$vgpr1 = V_MOV_B32_e32 0, implicit $exec
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$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
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S_ENDPGM
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...
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# GCN-LABEL: name: swap_virt_copy_condense
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# GCN: %0:vgpr_32, %1:vgpr_32 = V_SWAP_B32 %1, %0, implicit $exec
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---
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name: swap_virt_copy_condense
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = COPY %0
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%0 = COPY %1
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%1 = COPY %2
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...
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# GCN-LABEL: name: swap_virt_copy_sparse
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# GCN: %0:vgpr_32, %1:vgpr_32 = V_SWAP_B32 %1, %0, implicit $exec
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---
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name: swap_virt_copy_sparse
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = COPY %0
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S_NOP 0
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%0 = COPY %1
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S_NOP 0
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%1 = COPY %2
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...
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# GCN-LABEL: name: swap_virt_copy_subreg
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# GCN: %0.sub0:vreg_64, %1.sub0:vreg_64 = V_SWAP_B32 %1.sub0, %0.sub0, implicit $exec
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---
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name: swap_virt_copy_subreg
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vreg_64 }
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- { id: 2, class: vreg_64 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2.sub0 = COPY %0.sub0
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%2.sub1 = COPY %0.sub1
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%0.sub0 = COPY %1.sub0
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%0.sub1 = COPY %1.sub1
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%1.sub0 = COPY %2.sub0
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...
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# GCN-LABEL: name: swap_virt_mov
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# GCN: %0:vgpr_32, %1:vgpr_32 = V_SWAP_B32 %1, %0, implicit $exec
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---
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name: swap_virt_mov
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = V_MOV_B32_e32 %0, implicit $exec
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%0 = V_MOV_B32_e32 %1, implicit $exec
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%1 = V_MOV_B32_e32 %2, implicit $exec
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...
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# GCN-LABEL: name: swap_virt_read_x
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# GCN: bb.0:
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# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %2:vgpr_32 = COPY %0
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# GCN-NEXT: %3:vgpr_32 = COPY %0
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# GCN-NEXT: %0:vgpr_32 = COPY %1
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# GCN-NEXT: %1:vgpr_32 = COPY %2
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# GCN-NEXT: S_ENDPGM
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---
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name: swap_virt_read_x
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = COPY %0
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%3 = COPY %0
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%0 = COPY %1
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%1 = COPY %2
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S_ENDPGM
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...
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# GCN-LABEL: name: swap_virt_read_t_twice
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# GCN: bb.0:
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# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %2:vgpr_32 = COPY %0
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# GCN-NEXT: %3:vgpr_32 = COPY %2
|
||||
# GCN-NEXT: %0:vgpr_32, %1:vgpr_32 = V_SWAP_B32 %1, %0, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
---
|
||||
name: swap_virt_read_t_twice
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%3 = COPY %2
|
||||
%0 = COPY %1
|
||||
%1 = COPY %2
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_clobber_y
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:vgpr_32 = COPY %0
|
||||
# GCN-NEXT: %0:vgpr_32 = COPY %1
|
||||
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = COPY %2
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
---
|
||||
name: swap_virt_clobber_y
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = COPY %1
|
||||
%1 = IMPLICIT_DEF
|
||||
%1 = COPY %2
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_clobber_x1
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:vgpr_32 = COPY %0
|
||||
# GCN-NEXT: %0:vgpr_32 = COPY %1
|
||||
# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = COPY %2
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
---
|
||||
name: swap_virt_clobber_x1
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = COPY %1
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = COPY %2
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_clobber_x2
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:vgpr_32 = COPY %0
|
||||
# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %0:vgpr_32 = COPY %1
|
||||
# GCN-NEXT: %1:vgpr_32 = COPY %2
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
---
|
||||
name: swap_virt_clobber_x2
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = IMPLICIT_DEF
|
||||
%0 = COPY %1
|
||||
%1 = COPY %2
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_clobber_t
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:vgpr_32 = COPY %0
|
||||
# GCN-NEXT: %0:vgpr_32 = COPY %1
|
||||
# GCN-NEXT: %2:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = COPY %2
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
---
|
||||
name: swap_virt_clobber_t
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = COPY %1
|
||||
%2 = IMPLICIT_DEF
|
||||
%1 = COPY %2
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_copy_subreg_overlap_x_full
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2.sub0:vreg_64 = COPY %0.sub0
|
||||
# GCN-NEXT: %3:vreg_64 = COPY %0
|
||||
# GCN-NEXT: %0.sub0:vreg_64 = COPY %1.sub0
|
||||
# GCN-NEXT: %1.sub0:vreg_64 = COPY %2.sub0
|
||||
---
|
||||
name: swap_virt_copy_subreg_overlap_x_full
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_64 }
|
||||
- { id: 3, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub0 = COPY %0.sub0
|
||||
%3 = COPY %0
|
||||
%0.sub0 = COPY %1.sub0
|
||||
%1.sub0 = COPY %2.sub0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_copy_subreg_overlap_x_part
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2.sub0:vreg_64 = COPY %0.sub0
|
||||
# GCN-NEXT: %3:vreg_64 = COPY %0.sub0_sub1
|
||||
# GCN-NEXT: %0.sub0:vreg_128 = COPY %1.sub0
|
||||
# GCN-NEXT: %1.sub0:vreg_64 = COPY %2.sub0
|
||||
---
|
||||
name: swap_virt_copy_subreg_overlap_x_part
|
||||
registers:
|
||||
- { id: 0, class: vreg_128 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_64 }
|
||||
- { id: 3, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub0 = COPY %0.sub0
|
||||
%3 = COPY %0.sub0_sub1
|
||||
%0.sub0 = COPY %1.sub0
|
||||
%1.sub0 = COPY %2.sub0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_copy_subreg_wide_y
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2.sub0:vreg_64 = COPY %0.sub0
|
||||
# GCN-NEXT: %0.sub0:vreg_64 = COPY %1.sub0
|
||||
# GCN-NEXT: %1:vreg_64 = COPY %2
|
||||
---
|
||||
name: swap_virt_copy_subreg_wide_y
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub0 = COPY %0.sub0
|
||||
%0.sub0 = COPY %1.sub0
|
||||
%1 = COPY %2
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_b64
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %0.sub0:vreg_64, %1.sub0:vreg_64 = V_SWAP_B32 %1.sub0, %0.sub0, implicit $exec
|
||||
# GCN-NEXT: %0.sub1:vreg_64, %1.sub1:vreg_64 = V_SWAP_B32 %1.sub1, %0.sub1, implicit $exec
|
||||
---
|
||||
name: swap_virt_b64
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = COPY %1
|
||||
%1 = COPY %2
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_b128
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %0.sub0:vreg_128, %1.sub0:vreg_128 = V_SWAP_B32 %1.sub0, %0.sub0, implicit $exec
|
||||
# GCN-NEXT: %0.sub1:vreg_128, %1.sub1:vreg_128 = V_SWAP_B32 %1.sub1, %0.sub1, implicit $exec
|
||||
# GCN-NEXT: %0.sub2:vreg_128, %1.sub2:vreg_128 = V_SWAP_B32 %1.sub2, %0.sub2, implicit $exec
|
||||
# GCN-NEXT: %0.sub3:vreg_128, %1.sub3:vreg_128 = V_SWAP_B32 %1.sub3, %0.sub3, implicit $exec
|
||||
---
|
||||
name: swap_virt_b128
|
||||
registers:
|
||||
- { id: 0, class: vreg_128 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = COPY %1
|
||||
%1 = COPY %2
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_b128_sub0_1
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %0.sub0:vreg_128, %1.sub0:vreg_128 = V_SWAP_B32 %1.sub0, %0.sub0, implicit $exec
|
||||
# GCN-NEXT: %0.sub1:vreg_128, %1.sub1:vreg_128 = V_SWAP_B32 %1.sub1, %0.sub1, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
---
|
||||
name: swap_virt_b128_sub0_1
|
||||
registers:
|
||||
- { id: 0, class: vreg_128 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub0_sub1 = COPY %0.sub0_sub1
|
||||
%0.sub0_sub1 = COPY %1.sub0_sub1
|
||||
%1.sub0_sub1 = COPY %2.sub0_sub1
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_b128_sub2_3
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %0.sub2:vreg_128, %1.sub2:vreg_128 = V_SWAP_B32 %1.sub2, %0.sub2, implicit $exec
|
||||
# GCN-NEXT: %0.sub3:vreg_128, %1.sub3:vreg_128 = V_SWAP_B32 %1.sub3, %0.sub3, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
---
|
||||
name: swap_virt_b128_sub2_3
|
||||
registers:
|
||||
- { id: 0, class: vreg_128 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub2_sub3 = COPY %0.sub2_sub3
|
||||
%0.sub2_sub3 = COPY %1.sub2_sub3
|
||||
%1.sub2_sub3 = COPY %2.sub2_sub3
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
|
||||
# GCN-LABEL: name: swap_virt_s_to_s
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:sgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:sgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:sgpr_32 = COPY %0
|
||||
# GCN-NEXT: %0:sgpr_32 = COPY %1
|
||||
# GCN-NEXT: %1:sgpr_32 = COPY %2
|
||||
---
|
||||
name: swap_virt_s_to_s
|
||||
registers:
|
||||
- { id: 0, class: sgpr_32 }
|
||||
- { id: 1, class: sgpr_32 }
|
||||
- { id: 2, class: sgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = COPY %0
|
||||
%0 = COPY %1
|
||||
%1 = COPY %2
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_copy_subreg_impdef_super
|
||||
# GCN: %0.sub0:vreg_64, %1.sub0:vreg_64 = V_SWAP_B32 %1.sub0, %0.sub0, implicit $exec
|
||||
---
|
||||
name: swap_virt_copy_subreg_impdef_super
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub0 = COPY %0.sub0, implicit-def %2, implicit $exec
|
||||
%2.sub1 = COPY %0.sub1
|
||||
%0.sub0 = COPY %1.sub0
|
||||
%0.sub1 = COPY %1.sub1
|
||||
%1.sub0 = COPY %2.sub0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: swap_virt_copy_subreg_impuse_x
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: %0:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2.sub0:vreg_64 = COPY %0.sub0
|
||||
# GCN-NEXT: %2.sub1:vreg_64 = COPY %0.sub1
|
||||
# GCN-NEXT: %0.sub0:vreg_64 = COPY %1.sub0, implicit %0
|
||||
# GCN-NEXT: %0.sub1:vreg_64 = COPY %1.sub1
|
||||
# GCN-NEXT: %1.sub0:vreg_64 = COPY %2.sub0
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
---
|
||||
name: swap_virt_copy_subreg_impuse_x
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2.sub0 = COPY %0.sub0
|
||||
%2.sub1 = COPY %0.sub1
|
||||
%0.sub0 = COPY %1.sub0, implicit %0
|
||||
%0.sub1 = COPY %1.sub1
|
||||
%1.sub0 = COPY %2.sub0
|
||||
S_ENDPGM
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user