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[X86][Haswell][SchedModel] Add architecture specific scheduling models.

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Group: Integer instructions.
Sub-group: String instructions.

<rdar://problem/15607571>

llvm-svn: 215908
This commit is contained in:
Quentin Colombet 2014-08-18 17:55:19 +00:00
parent 4256d926fe
commit cc1d8c9134
1 changed files with 42 additions and 0 deletions
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42
lib/Target/X86/X86SchedHaswell.td
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@ -306,6 +306,10 @@ def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
let ResourceCycles = [3];
}
def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
let NumMicroOps = 2;
}
def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
let Latency = 1;
let ResourceCycles = [1, 2, 1];
@ -316,6 +320,11 @@ def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
let ResourceCycles = [2, 2, 1];
}
def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [2, 1];
}
def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
let Latency = 1;
let ResourceCycles = [3, 2, 1];
@ -874,4 +883,37 @@ def WriteINTO : SchedWriteRes<[]> {
}
def : InstRW<[WriteINTO], (instregex "INTO")>;
//-- String instructions --//
// LODSB/W.
def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
// LODSD/Q.
def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
// STOS.
def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> {
let NumMicroOps = 3;
}
def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>;
// MOVS.
def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 5;
let ResourceCycles = [2, 1, 2];
}
def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
// SCAS.
def : InstRW<[Write2P0156_P23], (instregex "SCAS(B|W|L|Q)")>;
// CMPS.
def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 5;
let ResourceCycles = [2, 3];
}
def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
} // SchedModel