RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Code Issues Projects Releases Wiki Activity

DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes

Browse Source 
DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two
mistakes:

1. It was checking the legality of scalar INT_TO_FP nodes and then generating
vector nodes.

2. It was passing the result value type to
TargetLoweringInfo::getOperationAction() when it should have been
passing the value type of the first operand.

llvm-svn: 171420
This commit is contained in:
Tom Stellard 2013-01-02 22:13:01 +00:00
parent 255beae3d9
commit ccd192dbc4
4 changed files with 42 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -8625,11 +8625,8 @@ SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
if (Opcode == ISD::DELETED_NODE &&
(Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
Opcode = Opc;
// If not supported by target, bail out.
if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal &&
TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom)
return SDValue();
}
if (Opc != Opcode)
return SDValue();
@ -8654,6 +8651,10 @@ SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
assert(SrcVT != MVT::Other && "Cannot determine source type!");
EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
return SDValue();
SmallVector<SDValue, 8> Opnds;
for (unsigned i = 0; i != NumInScalars; ++i) {
SDValue In = N->getOperand(i);

33
test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll Normal file
View File

@ -0,0 +1,33 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; This test is for a bug in
; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
; the wrong type was being passed to
; TargetLowering::getOperationAction() when checking the legality of
; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
%ptr = getelementptr i32 addrspace(1)* %in, i32 1
%sint = load i32 addrspace(1) * %in
%conv = sitofp i32 %sint to float
%0 = insertelement <4 x float> undef, float %conv, i32 0
%splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
store <4 x float> %splat, <4 x float> addrspace(1)* %out
ret void
}
;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
%ptr = getelementptr i32 addrspace(1)* %in, i32 1
%uint = load i32 addrspace(1) * %in
%conv = uitofp i32 %uint to float
%0 = insertelement <4 x float> undef, float %conv, i32 0
%splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
store <4 x float> %splat, <4 x float> addrspace(1)* %out
ret void
}

3
test/CodeGen/R600/vec4-expand.ll
View File

@ -1,6 +1,3 @@
; There are bugs in the DAGCombiner that prevent this test from passing.
; XFAIL: *
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

4
test/CodeGen/X86/cvtv2f32.ll
View File

@ -1,3 +1,7 @@
; A bug fix in the DAGCombiner made this test fail, so marking as xfail
; until this can be investigated further.
; XFAIL: *
; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s
define <2 x float> @foo(i32 %x, i32 %y, <2 x float> %v) {