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[X86][MMX] Improve support for folding fptosi from XMM to MMX
llvm-svn: 299338
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@ -28969,6 +28969,16 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
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DAG.getBitcast(MVT::v2i64, N00));
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}
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// Detect bitcasts from FP_TO_SINT to x86mmx.
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if (VT == MVT::x86mmx && SrcVT == MVT::v2i32 &&
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N0.getOpcode() == ISD::FP_TO_SINT) {
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SDLoc DL(N0);
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SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
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DAG.getUNDEF(MVT::v2i32));
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return DAG.getNode(X86ISD::MOVDQ2Q, DL, VT,
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DAG.getBitcast(MVT::v2i64, Res));
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}
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// Convert a bitcasted integer logic operation that has one bitcasted
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// floating-point operand into a floating-point logic operation. This may
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// create a load of a constant, but that is cheaper than materializing the
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@ -83,11 +83,9 @@ define void @fptosi_v2f64_v2i32(<2 x double>, <1 x i64>*) nounwind {
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $16, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movl 8(%ebp), %eax
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; X86-NEXT: cvttpd2dq %xmm0, %xmm0
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; X86-NEXT: movlpd %xmm0, {{[0-9]+}}(%esp)
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; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; X86-NEXT: cvttpd2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movl (%esp), %ecx
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@ -100,9 +98,7 @@ define void @fptosi_v2f64_v2i32(<2 x double>, <1 x i64>*) nounwind {
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;
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; X64-LABEL: fptosi_v2f64_v2i32:
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; X64: # BB#0:
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; X64-NEXT: cvttpd2dq %xmm0, %xmm0
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; X64-NEXT: movlpd %xmm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: movq -{{[0-9]+}}(%rsp), %mm0
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; X64-NEXT: cvttpd2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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