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[X86][MMX] Improve support for folding fptosi from XMM to MMX

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llvm-svn: 299338
This commit is contained in:
Simon Pilgrim 2017-04-02 17:45:41 +00:00
parent 0f4f942e8a
commit cd51879a46
2 changed files with 13 additions and 7 deletions
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10
lib/Target/X86/X86ISelLowering.cpp
View File

@ -28969,6 +28969,16 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
DAG.getBitcast(MVT::v2i64, N00));
}
// Detect bitcasts from FP_TO_SINT to x86mmx.
if (VT == MVT::x86mmx && SrcVT == MVT::v2i32 &&
N0.getOpcode() == ISD::FP_TO_SINT) {
SDLoc DL(N0);
SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
DAG.getUNDEF(MVT::v2i32));
return DAG.getNode(X86ISD::MOVDQ2Q, DL, VT,
DAG.getBitcast(MVT::v2i64, Res));
}
// Convert a bitcasted integer logic operation that has one bitcasted
// floating-point operand into a floating-point logic operation. This may
// create a load of a constant, but that is cheaper than materializing the

10
test/CodeGen/X86/mmx-cvt.ll
View File

@ -83,11 +83,9 @@ define void @fptosi_v2f64_v2i32(<2 x double>, <1 x i64>*) nounwind {
; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp
; X86-NEXT: subl $8, %esp
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: cvttpd2dq %xmm0, %xmm0
; X86-NEXT: movlpd %xmm0, {{[0-9]+}}(%esp)
; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0
; X86-NEXT: cvttpd2pi %xmm0, %mm0
; X86-NEXT: paddd %mm0, %mm0
; X86-NEXT: movq %mm0, (%esp)
; X86-NEXT: movl (%esp), %ecx
@ -100,9 +98,7 @@ define void @fptosi_v2f64_v2i32(<2 x double>, <1 x i64>*) nounwind {
;
; X64-LABEL: fptosi_v2f64_v2i32:
; X64: # BB#0:
; X64-NEXT: cvttpd2dq %xmm0, %xmm0
; X64-NEXT: movlpd %xmm0, -{{[0-9]+}}(%rsp)
; X64-NEXT: movq -{{[0-9]+}}(%rsp), %mm0
; X64-NEXT: cvttpd2pi %xmm0, %mm0
; X64-NEXT: paddd %mm0, %mm0
; X64-NEXT: movq %mm0, (%rdi)
; X64-NEXT: retq