RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.

Browse Source 
llvm-svn: 25004
This commit is contained in:
Evan Cheng 2005-12-24 09:48:35 +00:00
parent 1e6795bc0c
commit cd69c81c5e
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -57,9 +57,9 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Opc = X86::MOV16mr; Opc = X86::MOV16mr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpST64m; Opc = X86::FpST64m;
} else if (RC == &X86::V4F4RegClass) { } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
Opc = X86::MOVSSmr; Opc = X86::MOVSSmr;
} else if (RC == &X86::V2F8RegClass) { } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
Opc = X86::MOVSDmr; Opc = X86::MOVSDmr;
} else { } else {
assert(0 && "Unknown regclass"); assert(0 && "Unknown regclass");
@ -81,9 +81,9 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Opc = X86::MOV16rm; Opc = X86::MOV16rm;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpLD64m; Opc = X86::FpLD64m;
} else if (RC == &X86::V4F4RegClass) { } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
Opc = X86::MOVSSrm; Opc = X86::MOVSSrm;
} else if (RC == &X86::V2F8RegClass) { } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
Opc = X86::MOVSDrm; Opc = X86::MOVSDrm;
} else { } else {
assert(0 && "Unknown regclass"); assert(0 && "Unknown regclass");
@ -105,9 +105,9 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
Opc = X86::MOV16rr; Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV; Opc = X86::FpMOV;
} else if (RC == &X86::V4F4RegClass) { } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
Opc = X86::MOVSSrr; Opc = X86::MOVSSrr;
} else if (RC == &X86::V2F8RegClass) { } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
Opc = X86::MOVSDrr; Opc = X86::MOVSDrr;
} else { } else {
assert(0 && "Unknown regclass"); assert(0 && "Unknown regclass");