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This patch fixes the MC object emission of 'nop' for external function calls

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and also fixes the R_PPC64_TOC16 and R_PPC64_TOC16_DS relocation offset.
The 'nop' is needed so a restore TOC instruction (ld r2,40(r1)) can be placed
by the linker to correct restore the TOC of previous function.

Current code has two issues: it defines in PPCInstr64Bit.td file a LDinto_toc
and LDtoc_restore as a DSForm_1 with DS_RA=0 where it should be
DS=2 (the 8 bytes displacement of the TOC saving). It also wrongly emits a
MC intruction using an uint32_t value while the PPC::BL8_NOP_ELF
and PPC::BLA8_NOP_ELF are both uint64_t (because of the following 'nop').

This patch corrects the remaining ExecutionEngine using MCJIT:

ExecutionEngine/2002-12-16-ArgTest.ll
ExecutionEngine/2003-05-07-ArgumentTest.ll
ExecutionEngine/2005-12-02-TailCallBug.ll
ExecutionEngine/hello.ll
ExecutionEngine/hello2.ll
ExecutionEngine/test-call.ll

llvm-svn: 166682
This commit is contained in:
Adhemerval Zanella 2012-10-25 14:29:13 +00:00
parent 71c462aff2
commit cd87aee529
3 changed files with 17 additions and 7 deletions
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2
lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -146,6 +146,8 @@ adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
switch ((unsigned)Fixup.getKind()) {
case PPC::fixup_ppc_ha16:
case PPC::fixup_ppc_lo16:
case PPC::fixup_ppc_toc16:
case PPC::fixup_ppc_toc16_ds:
RelocOffset += 2;
break;
default:

14
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
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@ -75,11 +75,19 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
// BL8_NOPELF and BLA8_NOP_ELF is both size of 8 bacause of the
// following 'nop'.
unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
unsigned Opcode = MI.getOpcode();
if (Opcode == PPC::BL8_NOP_ELF || Opcode == PPC::BLA8_NOP_ELF)
Size = 8;
// Output the constant in big endian byte order.
for (unsigned i = 0; i != 4; ++i) {
OS << (char)(Bits >> 24);
int ShiftValue = (Size * 8) - 8;
for (unsigned i = 0; i != Size; ++i) {
OS << (char)(Bits >> ShiftValue);
Bits <<= 8;
}

8
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -639,13 +639,13 @@ def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
(PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
let hasSideEffects = 1 in {
let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg),
let RST = 2, DS = 2 in
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
"ld 2, 8($reg)", LdStLD,
[(PPCload_toc G8RC:$reg)]>, isPPC64;
let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
def LDtoc_restore : DSForm_1<58, 0, (outs), (ins),
let RST = 2, DS = 10, RA = 1 in
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
"ld 2, 40(1)", LdStLD,
[(PPCtoc_restore)]>, isPPC64;
}