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Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.

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llvm-svn: 137636
This commit is contained in:
Owen Anderson 2011-08-15 19:00:06 +00:00
parent 894585de33
commit cd94fca93d
2 changed files with 10 additions and 6 deletions
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13
lib/Target/ARM/ARMInstrThumb.td
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@ -113,6 +113,7 @@ def t_addrmode_rr : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
let EncoderMethod = "getThumbAddrModeRegRegOpValue";
let PrintMethod = "printThumbAddrModeRROperand";
let DecoderMethod = "DecodeThumbAddrModeRR";
let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
}
@ -620,17 +621,17 @@ defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
let AddedComplexity = 10 in
def tLDRSB : // A8.6.80
T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
AddrModeT1_1, IIC_iLoad_bh_r,
"ldrsb", "\t$dst, $addr",
[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
"ldrsb", "\t$Rt, $addr",
[(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
let AddedComplexity = 10 in
def tLDRSH : // A8.6.84
T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
AddrModeT1_2, IIC_iLoad_bh_r,
"ldrsh", "\t$dst, $addr",
[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
"ldrsh", "\t$Rt, $addr",
[(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
let canFoldAsLoad = 1 in
def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,

3
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -268,3 +268,6 @@
# CHECK: vadd.f32 q0, q1, q2
0x02 0xef 0x44 0x0d
# CHECK: ldrsb r1, [r0, r0]
0x01 0x56