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[NFC][InstCombine] More tests for PR42563 "Dropping pointless masking before left shift"

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For patterns c/d/e we too can deal with the pattern even if we can't
just drop the mask, we can just apply it afterwars:
   https://rise4fun.com/Alive/gslRa

llvm-svn: 372244
This commit is contained in:
Roman Lebedev 2019-09-18 18:38:32 +00:00
parent 1c646a78c0
commit cdaf6001ac
7 changed files with 313 additions and 67 deletions
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98
test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll Normal file
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@ -0,0 +1,98 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -instcombine -S | FileCheck %s
; If we have some pattern that leaves only some low bits set, and then performs
; left-shift of those bits, we can combine those two shifts into a shift+mask.
; There are many variants to this pattern:
; c) (x & (-1 >> maskNbits)) << shiftNbits
; simplify to:
; (x << shiftNbits) & (-1 >> ((-(maskNbits+shiftNbits))+32))
; Simple tests.
declare void @use32(i32)
define i32 @t0_basic(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t0_basic(
; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = lshr i32 -1, %nbits
%t1 = and i32 %t0, %x
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t3
}
; Vectors
declare void @use8xi32(<8 x i32>)
define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t1_vec_splat(
; CHECK-NEXT: [[T0:%.*]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and <8 x i32> [[T0]], [[X:%.*]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl <8 x i32> [[T1]], [[T2]]
; CHECK-NEXT: ret <8 x i32> [[T3]]
;
%t0 = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
%t1 = and <8 x i32> %t0, %x
%t2 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t2)
%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
ret <8 x i32> %t3
}
define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t1_vec_nonsplat(
; CHECK-NEXT: [[T0:%.*]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and <8 x i32> [[T0]], [[X:%.*]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl <8 x i32> [[T1]], [[T2]]
; CHECK-NEXT: ret <8 x i32> [[T3]]
;
%t0 = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
%t1 = and <8 x i32> %t0, %x
%t2 = add <8 x i32> %nbits, <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t2)
%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
ret <8 x i32> %t3
}
; Extra uses.
define i32 @n3_extrause(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n3_extrause(
; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = lshr i32 -1, %nbits
%t1 = and i32 %t0, %x
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1) ; BAD
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t3
}

114
test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll Normal file
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@ -0,0 +1,114 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -instcombine -S | FileCheck %s
; If we have some pattern that leaves only some low bits set, and then performs
; left-shift of those bits, we can combine those two shifts into a shift+mask.
; There are many variants to this pattern:
; d) (x & ((-1 << maskNbits) >> maskNbits)) << shiftNbits
; simplify to:
; (x << shiftNbits) & (-1 >> ((-(maskNbits+shiftNbits))+32))
; Simple tests.
declare void @use32(i32)
define i32 @t0_basic(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t0_basic(
; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T3]])
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
; CHECK-NEXT: ret i32 [[T4]]
;
%t0 = shl i32 -1, %nbits
%t1 = lshr i32 %t0, %nbits
%t2 = and i32 %t1, %x
%t3 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t3)
%t4 = shl i32 %t2, %t3 ; shift is smaller than mask
ret i32 %t4
}
; Vectors
declare void @use8xi32(<8 x i32>)
define <8 x i32> @t2_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t2_vec_splat(
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = and <8 x i32> [[T1]], [[X:%.*]]
; CHECK-NEXT: [[T3:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]])
; CHECK-NEXT: [[T4:%.*]] = shl <8 x i32> [[T2]], [[T3]]
; CHECK-NEXT: ret <8 x i32> [[T4]]
;
%t0 = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
%t1 = lshr <8 x i32> %t0, %nbits
%t2 = and <8 x i32> %t1, %x
%t3 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t1)
call void @use8xi32(<8 x i32> %t3)
%t4 = shl <8 x i32> %t2, %t3 ; shift is smaller than mask
ret <8 x i32> %t4
}
define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t2_vec_nonsplat(
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = and <8 x i32> [[T1]], [[X:%.*]]
; CHECK-NEXT: [[T3:%.*]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]])
; CHECK-NEXT: [[T4:%.*]] = shl <8 x i32> [[T2]], [[T3]]
; CHECK-NEXT: ret <8 x i32> [[T4]]
;
%t0 = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
%t1 = lshr <8 x i32> %t0, %nbits
%t2 = and <8 x i32> %t1, %x
%t3 = add <8 x i32> %nbits, <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t1)
call void @use8xi32(<8 x i32> %t3)
%t4 = shl <8 x i32> %t2, %t3 ; shift is smaller than mask
ret <8 x i32> %t4
}
; Extra uses.
define i32 @n3_extrause(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n3_extrause(
; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: call void @use32(i32 [[T3]])
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
; CHECK-NEXT: ret i32 [[T4]]
;
%t0 = shl i32 -1, %nbits
%t1 = lshr i32 %t0, %nbits
%t2 = and i32 %t1, %x
%t3 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t2) ; BAD
call void @use32(i32 %t3)
%t4 = shl i32 %t2, %t3 ; shift is smaller than mask
ret i32 %t4
}

98
test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll Normal file
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@ -0,0 +1,98 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -instcombine -S | FileCheck %s
; If we have some pattern that leaves only some low bits set, and then performs
; left-shift of those bits, we can combine those two shifts into a shift+mask.
; There are many variants to this pattern:
; e) ((x << maskNbits) l>> maskNbits) << shiftNbits
; simplify to:
; (x << shiftNbits) & (-1 >> ((-(maskNbits+shiftNbits))+32))
; Simple tests.
declare void @use32(i32)
define i32 @t0_basic(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t0_basic(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = shl i32 %x, %nbits
%t1 = lshr i32 %t0, %nbits
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t3
}
; Vectors
declare void @use8xi32(<8 x i32>)
define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t1_vec_splat(
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl <8 x i32> [[T1]], [[T2]]
; CHECK-NEXT: ret <8 x i32> [[T3]]
;
%t0 = shl <8 x i32> %x, %nbits
%t1 = lshr <8 x i32> %t0, %nbits
%t2 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t2)
%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
ret <8 x i32> %t3
}
define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t1_vec_nonsplat(
; CHECK-NEXT: [[T0:%.*]] = shl <8 x i32> [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl <8 x i32> [[T1]], [[T2]]
; CHECK-NEXT: ret <8 x i32> [[T3]]
;
%t0 = shl <8 x i32> %x, %nbits
%t1 = lshr <8 x i32> %t0, %nbits
%t2 = add <8 x i32> %nbits, <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t2)
%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
ret <8 x i32> %t3
}
; Extra uses.
define i32 @n3_extrause(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n3_extrause(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = shl i32 %x, %nbits
%t1 = lshr i32 %t0, %nbits
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1) ; BAD
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t3
}

20
test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
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@ -281,23 +281,3 @@ define i32 @n12_not_minus_one(i32 %x, i32 %nbits) {
%t2 = shl i32 %t1, %nbits
ret i32 %t2
}
define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n13_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = lshr i32 -1, %nbits
%t1 = and i32 %t0, %x
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t2
}

23
test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
View File

@ -361,26 +361,3 @@ define i32 @n13_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
%t3 = shl i32 %t2, %nbits1
ret i32 %t3
}
define i32 @n14_shamt_is_smaller(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n14_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
; CHECK-NEXT: ret i32 [[T4]]
;
%t0 = shl i32 -1, %nbits
%t1 = lshr i32 %t0, %nbits
%t2 = and i32 %t1, %x
%t3 = add i32 %nbits, -1 ; shift is smaller than mask
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t2)
%t4 = shl i32 %t2, %t3
ret i32 %t4
}

20
test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
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@ -234,23 +234,3 @@ define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
%t2 = shl i32 %t1, %nbits1
ret i32 %t2
}
define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n11_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = shl i32 %x, %nbits
%t1 = lshr i32 %t0, %nbits
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t2
}

7
test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
View File

@ -241,16 +241,15 @@ define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: ret i32 [[T2]]
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
ret i32 %t2
ret i32 %t3
}