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[X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classes
Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions. Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour. llvm-svn: 331672
This commit is contained in:
Simon Pilgrim
parent
3bb5b23c4a
commit
cdb89ed3dc
@ -2672,9 +2672,8 @@ multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
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EVEX_CD8<64, CD8VT1>, VEX_W;
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}
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// FIXME: Is there a better scheduler class for VFPCLASS?
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defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
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X86Vfpclasss, SchedWriteFAdd, HasDQI>,
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X86Vfpclasss, SchedWriteFCmp, HasDQI>,
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AVX512AIi8Base, EVEX;
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//-----------------------------------------------------------------
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@ -1854,12 +1854,12 @@ let ExeDomain = SSEPackedSingle in
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defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
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"cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SchedWriteFCmp.Scl>, XS, VEX_4V, VEX_LIG, VEX_WIG;
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SchedWriteFCmpSizes.PS.Scl>, XS, VEX_4V, VEX_LIG, VEX_WIG;
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let ExeDomain = SSEPackedDouble in
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defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
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"cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SchedWriteFCmp.Scl>, // same latency as 32 bit compare
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SchedWriteFCmpSizes.PD.Scl>,
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XD, VEX_4V, VEX_LIG, VEX_WIG;
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let Constraints = "$src1 = $dst" in {
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@ -1867,12 +1867,12 @@ let Constraints = "$src1 = $dst" in {
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defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
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"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
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"cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}",
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SchedWriteFCmp.Scl>, XS;
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SchedWriteFCmpSizes.PS.Scl>, XS;
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let ExeDomain = SSEPackedDouble in
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defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
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"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
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"cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
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SchedWriteFCmp.Scl>, XD;
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SchedWriteFCmpSizes.PD.Scl>, XD;
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}
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multiclass sse12_cmp_scalar_int<Operand memop, Operand CC,
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@ -1896,21 +1896,21 @@ let isCodeGenOnly = 1 in {
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let ExeDomain = SSEPackedSingle in
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defm VCMPSS : sse12_cmp_scalar_int<ssmem, AVXCC, int_x86_sse_cmp_ss,
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"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
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SchedWriteFCmp.Scl, sse_load_f32>, XS, VEX_4V;
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SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, XS, VEX_4V;
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let ExeDomain = SSEPackedDouble in
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defm VCMPSD : sse12_cmp_scalar_int<sdmem, AVXCC, int_x86_sse2_cmp_sd,
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"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
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SchedWriteFCmp.Scl, sse_load_f64>, // same latency as f32
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SchedWriteFCmpSizes.PD.Scl, sse_load_f64>,
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XD, VEX_4V;
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let Constraints = "$src1 = $dst" in {
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let ExeDomain = SSEPackedSingle in
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defm CMPSS : sse12_cmp_scalar_int<ssmem, SSECC, int_x86_sse_cmp_ss,
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"cmp${cc}ss\t{$src, $dst|$dst, $src}",
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SchedWriteFCmp.Scl, sse_load_f32>, XS;
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SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, XS;
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let ExeDomain = SSEPackedDouble in
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defm CMPSD : sse12_cmp_scalar_int<sdmem, SSECC, int_x86_sse2_cmp_sd,
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"cmp${cc}sd\t{$src, $dst|$dst, $src}",
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SchedWriteFCmp.Scl, sse_load_f64>, XD;
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SchedWriteFCmpSizes.PD.Scl, sse_load_f64>, XD;
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}
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}
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@ -2030,28 +2030,28 @@ multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
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defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, v4f32,
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"cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SchedWriteFCmp.XMM, SSEPackedSingle, loadv4f32>, PS, VEX_4V, VEX_WIG;
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SchedWriteFCmpSizes.PS.XMM, SSEPackedSingle, loadv4f32>, PS, VEX_4V, VEX_WIG;
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defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, v2f64,
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"cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SchedWriteFCmp.XMM, SSEPackedDouble, loadv2f64>, PD, VEX_4V, VEX_WIG;
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SchedWriteFCmpSizes.PD.XMM, SSEPackedDouble, loadv2f64>, PD, VEX_4V, VEX_WIG;
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defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, v8f32,
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"cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SchedWriteFCmp.YMM, SSEPackedSingle, loadv8f32>, PS, VEX_4V, VEX_L, VEX_WIG;
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SchedWriteFCmpSizes.PS.YMM, SSEPackedSingle, loadv8f32>, PS, VEX_4V, VEX_L, VEX_WIG;
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defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, v4f64,
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"cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SchedWriteFCmp.YMM, SSEPackedDouble, loadv4f64>, PD, VEX_4V, VEX_L, VEX_WIG;
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SchedWriteFCmpSizes.PD.YMM, SSEPackedDouble, loadv4f64>, PD, VEX_4V, VEX_L, VEX_WIG;
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, v4f32,
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"cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
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"cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
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SchedWriteFCmp.XMM, SSEPackedSingle, memopv4f32>, PS;
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SchedWriteFCmpSizes.PS.XMM, SSEPackedSingle, memopv4f32>, PS;
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defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, v2f64,
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"cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
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"cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
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SchedWriteFCmp.XMM, SSEPackedDouble, memopv2f64>, PD;
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SchedWriteFCmpSizes.PD.XMM, SSEPackedDouble, memopv2f64>, PD;
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}
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def CommutableCMPCC : PatLeaf<(imm), [{
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@ -4438,28 +4438,28 @@ multiclass sse3_addsub<string OpcodeStr, ValueType vt, RegisterClass RC,
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let Predicates = [HasAVX] in {
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let ExeDomain = SSEPackedSingle in {
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defm VADDSUBPS : sse3_addsub<"vaddsubps", v4f32, VR128, f128mem,
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SchedWriteFAdd.XMM, loadv4f32, 0>,
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SchedWriteFAddSizes.PS.XMM, loadv4f32, 0>,
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XD, VEX_4V, VEX_WIG;
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defm VADDSUBPSY : sse3_addsub<"vaddsubps", v8f32, VR256, f256mem,
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SchedWriteFAdd.YMM, loadv8f32, 0>,
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SchedWriteFAddSizes.PS.YMM, loadv8f32, 0>,
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XD, VEX_4V, VEX_L, VEX_WIG;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VADDSUBPD : sse3_addsub<"vaddsubpd", v2f64, VR128, f128mem,
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SchedWriteFAdd.XMM, loadv2f64, 0>,
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SchedWriteFAddSizes.PD.XMM, loadv2f64, 0>,
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PD, VEX_4V, VEX_WIG;
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defm VADDSUBPDY : sse3_addsub<"vaddsubpd", v4f64, VR256, f256mem,
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SchedWriteFAdd.YMM, loadv4f64, 0>,
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SchedWriteFAddSizes.PD.YMM, loadv4f64, 0>,
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PD, VEX_4V, VEX_L, VEX_WIG;
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}
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}
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let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
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let ExeDomain = SSEPackedSingle in
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defm ADDSUBPS : sse3_addsub<"addsubps", v4f32, VR128, f128mem,
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SchedWriteFAdd.XMM, memopv4f32>, XD;
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SchedWriteFAddSizes.PS.XMM, memopv4f32>, XD;
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let ExeDomain = SSEPackedDouble in
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defm ADDSUBPD : sse3_addsub<"addsubpd", v2f64, VR128, f128mem,
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SchedWriteFAdd.XMM, memopv2f64>, PD;
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SchedWriteFAddSizes.PD.XMM, memopv2f64>, PD;
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}
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//===---------------------------------------------------------------------===//
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@ -155,13 +155,28 @@ def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
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def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
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def : WriteRes<WriteFMove, [BWPort5]>;
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defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub.
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defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
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defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare.
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defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
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defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags.
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defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
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defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
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defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub.
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defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM).
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defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
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defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub.
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defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM).
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defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
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defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare.
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defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM).
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defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
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defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare.
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defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM).
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defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
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defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags.
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defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
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defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
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defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
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defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
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defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
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defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
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//defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
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defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
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@ -149,13 +149,28 @@ def : WriteRes<WriteFLoad, [HWPort23]> { let Latency = 5; }
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def : WriteRes<WriteFMove, [HWPort5]>;
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defm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>;
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defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 6>;
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defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>;
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defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 6>;
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defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>;
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defm : HWWriteResPair<WriteFCom, [HWPort1], 3>;
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defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 6>;
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defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>;
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defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>;
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defm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>;
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defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>;
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defm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>;
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defm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>;
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defm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>;
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defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>;
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defm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>;
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defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>;
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defm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>;
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defm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>;
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defm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>;
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defm : HWWriteResPair<WriteFCom, [HWPort1], 3>;
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defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>;
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defm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>;
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defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>;
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defm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>;
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defm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>;
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defm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>;
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defm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>;
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defm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>;
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@ -882,17 +897,7 @@ def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
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}
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def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPI2PSirm",
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"PDEP(32|64)rm",
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"PEXT(32|64)rm",
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"(V?)ADDSDrm",
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"(V?)ADDSSrm",
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"(V?)CMPSDrm",
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"(V?)CMPSSrm",
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"(V?)MAX(C?)SDrm",
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"(V?)MAX(C?)SSrm",
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"(V?)MIN(C?)SDrm",
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"(V?)MIN(C?)SSrm",
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"(V?)SUBSDrm",
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"(V?)SUBSSrm")>;
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"PEXT(32|64)rm")>;
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def HWWriteResGroup12_1 : SchedWriteRes<[HWPort1,HWPort0156,HWPort23]> {
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let Latency = 8;
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@ -1658,14 +1663,6 @@ def HWWriteResGroup91_5 : SchedWriteRes<[HWPort0,HWPort23]> {
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}
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def: InstRW<[HWWriteResGroup91_5], (instregex "MMX_PSADBWirm")>;
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def HWWriteResGroup92_2 : SchedWriteRes<[HWPort01,HWPort23]> {
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let Latency = 10;
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let NumMicroOps = 2;
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let ResourceCycles = [1,1];
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}
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def: InstRW<[HWWriteResGroup92_2], (instregex "(V?)MULSDrm",
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"(V?)MULSSrm")>;
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def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
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let Latency = 5;
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let NumMicroOps = 3;
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@ -139,13 +139,28 @@ def : WriteRes<WriteFLoad, [SBPort23]> { let Latency = 6; }
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def : WriteRes<WriteFMove, [SBPort5]>;
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defm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>;
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defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>;
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defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>;
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defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>;
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defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>;
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defm : SBWriteResPair<WriteFCom, [SBPort1], 3>;
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defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>;
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defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>;
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defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>;
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defm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>;
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defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>;
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defm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>;
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defm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>;
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defm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>;
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defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>;
|
||||
defm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>;
|
||||
|
||||
defm : SBWriteResPair<WriteFCom, [SBPort1], 3>;
|
||||
|
||||
defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>;
|
||||
defm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>;
|
||||
|
||||
defm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
|
||||
defm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
|
||||
|
||||
@ -152,13 +152,28 @@ def : WriteRes<WriteFStore, [SKLPort237, SKLPort4]>;
|
||||
def : WriteRes<WriteFMove, [SKLPort015]>;
|
||||
defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>;
|
||||
|
||||
defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 6>; // Floating point add/sub.
|
||||
defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
|
||||
defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 6>; // Floating point compare.
|
||||
defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; // Floating point compare (YMM/ZMM).
|
||||
defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags.
|
||||
defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 6>; // Floating point multiplication.
|
||||
defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
|
||||
defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub.
|
||||
defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; // Floating point add/sub (XMM).
|
||||
defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
|
||||
defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub.
|
||||
defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; // Floating point double add/sub (XMM).
|
||||
defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; // Floating point double add/sub (YMM/ZMM).
|
||||
|
||||
defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare.
|
||||
defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; // Floating point compare (XMM).
|
||||
defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; // Floating point compare (YMM/ZMM).
|
||||
defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare.
|
||||
defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; // Floating point double compare (XMM).
|
||||
defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; // Floating point double compare (YMM/ZMM).
|
||||
|
||||
defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags.
|
||||
|
||||
defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication.
|
||||
defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; // Floating point multiplication (XMM).
|
||||
defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
|
||||
defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication.
|
||||
defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; // Floating point double multiplication (XMM).
|
||||
defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; // Floating point double multiplication (YMM/ZMM).
|
||||
|
||||
defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
|
||||
//defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; // Floating point division (XMM).
|
||||
@ -1473,24 +1488,6 @@ def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm",
|
||||
"VPMOVSXWDYrm",
|
||||
"VPMOVZXWDYrm")>;
|
||||
|
||||
def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 2;
|
||||
let ResourceCycles = [1,1];
|
||||
}
|
||||
def: InstRW<[SKLWriteResGroup122], (instregex "(V?)ADDSDrm",
|
||||
"(V?)ADDSSrm",
|
||||
"(V?)CMPSDrm",
|
||||
"(V?)CMPSSrm",
|
||||
"(V?)MAX(C?)SDrm",
|
||||
"(V?)MAX(C?)SSrm",
|
||||
"(V?)MIN(C?)SDrm",
|
||||
"(V?)MIN(C?)SSrm",
|
||||
"(V?)MULSDrm",
|
||||
"(V?)MULSSrm",
|
||||
"(V?)SUBSDrm",
|
||||
"(V?)SUBSSrm")>;
|
||||
|
||||
def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 2;
|
||||
|
||||
@ -152,13 +152,28 @@ def : WriteRes<WriteFStore, [SKXPort237, SKXPort4]>;
|
||||
def : WriteRes<WriteFMove, [SKXPort015]>;
|
||||
defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;
|
||||
|
||||
defm : SKXWriteResPair<WriteFAdd, [SKXPort015], 4, [1], 1, 6>; // Floating point add/sub.
|
||||
defm : SKXWriteResPair<WriteFAddY,[SKXPort015], 4, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
|
||||
defm : SKXWriteResPair<WriteFCmp, [SKXPort015], 4, [1], 1, 6>; // Floating point compare.
|
||||
defm : SKXWriteResPair<WriteFCmpY,[SKXPort015], 4, [1], 1, 7>; // Floating point compare (YMM/ZMM).
|
||||
defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags.
|
||||
defm : SKXWriteResPair<WriteFMul, [SKXPort015], 4, [1], 1, 6>; // Floating point multiplication.
|
||||
defm : SKXWriteResPair<WriteFMulY,[SKXPort015], 4, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
|
||||
defm : SKXWriteResPair<WriteFAdd, [SKXPort015], 4, [1], 1, 5>; // Floating point add/sub.
|
||||
defm : SKXWriteResPair<WriteFAddX, [SKXPort015], 4, [1], 1, 6>; // Floating point add/sub (XMM).
|
||||
defm : SKXWriteResPair<WriteFAddY, [SKXPort015], 4, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
|
||||
defm : SKXWriteResPair<WriteFAdd64, [SKXPort015], 4, [1], 1, 5>; // Floating point double add/sub.
|
||||
defm : SKXWriteResPair<WriteFAdd64X, [SKXPort015], 4, [1], 1, 6>; // Floating point double add/sub (XMM).
|
||||
defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort015], 4, [1], 1, 7>; // Floating point double add/sub (YMM/ZMM).
|
||||
|
||||
defm : SKXWriteResPair<WriteFCmp, [SKXPort015], 4, [1], 1, 5>; // Floating point compare.
|
||||
defm : SKXWriteResPair<WriteFCmpX, [SKXPort015], 4, [1], 1, 6>; // Floating point compare (XMM).
|
||||
defm : SKXWriteResPair<WriteFCmpY, [SKXPort015], 4, [1], 1, 7>; // Floating point compare (YMM/ZMM).
|
||||
defm : SKXWriteResPair<WriteFCmp64, [SKXPort015], 4, [1], 1, 5>; // Floating point double compare.
|
||||
defm : SKXWriteResPair<WriteFCmp64X, [SKXPort015], 4, [1], 1, 6>; // Floating point double compare (XMM).
|
||||
defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort015], 4, [1], 1, 7>; // Floating point double compare (YMM/ZMM).
|
||||
|
||||
defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags.
|
||||
|
||||
defm : SKXWriteResPair<WriteFMul, [SKXPort015], 4, [1], 1, 5>; // Floating point multiplication.
|
||||
defm : SKXWriteResPair<WriteFMulX, [SKXPort015], 4, [1], 1, 6>; // Floating point multiplication (XMM).
|
||||
defm : SKXWriteResPair<WriteFMulY, [SKXPort015], 4, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
|
||||
defm : SKXWriteResPair<WriteFMul64, [SKXPort015], 4, [1], 1, 5>; // Floating point double multiplication.
|
||||
defm : SKXWriteResPair<WriteFMul64X, [SKXPort015], 4, [1], 1, 6>; // Floating point double multiplication (XMM).
|
||||
defm : SKXWriteResPair<WriteFMul64Y, [SKXPort015], 4, [1], 1, 7>; // Floating point double multiplication (YMM/ZMM).
|
||||
|
||||
defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
|
||||
//defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. // Floating point division (XMM).
|
||||
@ -2472,20 +2487,8 @@ def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
|
||||
}
|
||||
def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVTPS2PIirm",
|
||||
"MMX_CVTTPS2PIirm",
|
||||
"(V?)ADDSDrm",
|
||||
"(V?)ADDSSrm",
|
||||
"(V?)CMPSDrm",
|
||||
"(V?)CMPSSrm",
|
||||
"VCVTPH2PSrm",
|
||||
"(V?)CVTPS2PDrm",
|
||||
"(V?)MAX(C?)SDrm",
|
||||
"(V?)MAX(C?)SSrm",
|
||||
"(V?)MIN(C?)SDrm",
|
||||
"(V?)MIN(C?)SSrm",
|
||||
"(V?)MULSDrm",
|
||||
"(V?)MULSSrm",
|
||||
"(V?)SUBSDrm",
|
||||
"(V?)SUBSSrm")>;
|
||||
"(V?)CVTPS2PDrm")>;
|
||||
|
||||
def SKXWriteResGroup138 : SchedWriteRes<[SKXPort0,SKXPort015]> {
|
||||
let Latency = 9;
|
||||
|
||||
@ -105,24 +105,37 @@ def WriteZero : SchedWrite;
|
||||
defm WriteJump : X86SchedWritePair;
|
||||
|
||||
// Floating point. This covers both scalar and vector operations.
|
||||
def WriteFLoad : SchedWrite;
|
||||
def WriteFStore : SchedWrite;
|
||||
def WriteFMove : SchedWrite;
|
||||
defm WriteFAdd : X86SchedWritePair; // Floating point add/sub.
|
||||
defm WriteFAddY : X86SchedWritePair; // Floating point add/sub (YMM/ZMM).
|
||||
defm WriteFCmp : X86SchedWritePair; // Floating point compare.
|
||||
defm WriteFCmpY : X86SchedWritePair; // Floating point compare (YMM/ZMM).
|
||||
defm WriteFCom : X86SchedWritePair; // Floating point compare to flags.
|
||||
defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
|
||||
defm WriteFMulY : X86SchedWritePair; // Floating point multiplication (YMM/ZMM).
|
||||
def WriteFLoad : SchedWrite;
|
||||
def WriteFStore : SchedWrite;
|
||||
def WriteFMove : SchedWrite;
|
||||
|
||||
defm WriteFAdd : X86SchedWritePair; // Floating point add/sub.
|
||||
defm WriteFAddX : X86SchedWritePair; // Floating point add/sub (XMM).
|
||||
defm WriteFAddY : X86SchedWritePair; // Floating point add/sub (YMM/ZMM).
|
||||
defm WriteFAdd64 : X86SchedWritePair; // Floating point double add/sub.
|
||||
defm WriteFAdd64X : X86SchedWritePair; // Floating point double add/sub (XMM).
|
||||
defm WriteFAdd64Y : X86SchedWritePair; // Floating point double add/sub (YMM/ZMM).
|
||||
defm WriteFCmp : X86SchedWritePair; // Floating point compare.
|
||||
defm WriteFCmpX : X86SchedWritePair; // Floating point compare (XMM).
|
||||
defm WriteFCmpY : X86SchedWritePair; // Floating point compare (YMM/ZMM).
|
||||
defm WriteFCmp64 : X86SchedWritePair; // Floating point double compare.
|
||||
defm WriteFCmp64X : X86SchedWritePair; // Floating point double compare (XMM).
|
||||
defm WriteFCmp64Y : X86SchedWritePair; // Floating point double compare (YMM/ZMM).
|
||||
defm WriteFCom : X86SchedWritePair; // Floating point compare to flags.
|
||||
defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
|
||||
defm WriteFMulX : X86SchedWritePair; // Floating point multiplication (XMM).
|
||||
defm WriteFMulY : X86SchedWritePair; // Floating point multiplication (YMM/ZMM).
|
||||
defm WriteFMul64 : X86SchedWritePair; // Floating point double multiplication.
|
||||
defm WriteFMul64X : X86SchedWritePair; // Floating point double multiplication (XMM).
|
||||
defm WriteFMul64Y : X86SchedWritePair; // Floating point double multiplication (YMM/ZMM).
|
||||
defm WriteFDiv : X86SchedWritePair; // Floating point division.
|
||||
defm WriteFDivX : X86SchedWritePair; // Floating point division (XMM).
|
||||
defm WriteFDivY : X86SchedWritePair; // Floating point division (YMM).
|
||||
defm WriteFDivZ : X86SchedWritePair; // Floating point division (ZMM).
|
||||
defm WriteFDiv64 : X86SchedWritePair; // Floating point division.
|
||||
defm WriteFDiv64X : X86SchedWritePair; // Floating point division (XMM).
|
||||
defm WriteFDiv64Y : X86SchedWritePair; // Floating point division (YMM).
|
||||
defm WriteFDiv64Z : X86SchedWritePair; // Floating point division (ZMM).
|
||||
defm WriteFDiv64 : X86SchedWritePair; // Floating point double division.
|
||||
defm WriteFDiv64X : X86SchedWritePair; // Floating point double division (XMM).
|
||||
defm WriteFDiv64Y : X86SchedWritePair; // Floating point double division (YMM).
|
||||
defm WriteFDiv64Z : X86SchedWritePair; // Floating point double division (ZMM).
|
||||
defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
|
||||
defm WriteFSqrtX : X86SchedWritePair; // Floating point square root (XMM).
|
||||
defm WriteFSqrtY : X86SchedWritePair; // Floating point square root (YMM).
|
||||
@ -267,15 +280,19 @@ def WriteNop : SchedWrite;
|
||||
|
||||
// Vector width wrappers.
|
||||
def SchedWriteFAdd
|
||||
: X86SchedWriteWidths<WriteFAdd, WriteFAdd, WriteFAddY, WriteFAddY>;
|
||||
: X86SchedWriteWidths<WriteFAdd, WriteFAddX, WriteFAddY, WriteFAddY>;
|
||||
def SchedWriteFAdd64
|
||||
: X86SchedWriteWidths<WriteFAdd64, WriteFAdd64X, WriteFAdd64Y, WriteFAdd64Y>;
|
||||
def SchedWriteFHAdd
|
||||
: X86SchedWriteWidths<WriteFHAdd, WriteFHAdd, WriteFHAddY, WriteFHAddY>;
|
||||
def SchedWriteFCmp
|
||||
: X86SchedWriteWidths<WriteFCmp, WriteFCmp, WriteFCmpY, WriteFCmpY>;
|
||||
: X86SchedWriteWidths<WriteFCmp, WriteFCmpX, WriteFCmpY, WriteFCmpY>;
|
||||
def SchedWriteFCmp64
|
||||
: X86SchedWriteWidths<WriteFCmp64, WriteFCmp64X, WriteFCmp64Y, WriteFCmp64Y>;
|
||||
def SchedWriteFMul
|
||||
: X86SchedWriteWidths<WriteFMul, WriteFMul, WriteFMulY, WriteFMulY>;
|
||||
: X86SchedWriteWidths<WriteFMul, WriteFMulX, WriteFMulY, WriteFMulY>;
|
||||
def SchedWriteFMul64
|
||||
: X86SchedWriteWidths<WriteFMul, WriteFMul, WriteFMulY, WriteFMulY>;
|
||||
: X86SchedWriteWidths<WriteFMul64, WriteFMul64X, WriteFMul64Y, WriteFMul64Y>;
|
||||
def SchedWriteFMA
|
||||
: X86SchedWriteWidths<WriteFMA, WriteFMAX, WriteFMAY, WriteFMAY>;
|
||||
def SchedWriteDPPD
|
||||
@ -356,9 +373,9 @@ def SchedWriteVarBlend
|
||||
|
||||
// Vector size wrappers.
|
||||
def SchedWriteFAddSizes
|
||||
: X86SchedWriteSizes<SchedWriteFAdd, SchedWriteFAdd>;
|
||||
: X86SchedWriteSizes<SchedWriteFAdd, SchedWriteFAdd64>;
|
||||
def SchedWriteFCmpSizes
|
||||
: X86SchedWriteSizes<SchedWriteFCmp, SchedWriteFCmp>;
|
||||
: X86SchedWriteSizes<SchedWriteFCmp, SchedWriteFCmp64>;
|
||||
def SchedWriteFMulSizes
|
||||
: X86SchedWriteSizes<SchedWriteFMul, SchedWriteFMul64>;
|
||||
def SchedWriteFDivSizes
|
||||
|
||||
@ -204,12 +204,24 @@ def : WriteRes<WriteFMove, [AtomPort01]>;
|
||||
defm : X86WriteRes<WriteEMMS,[AtomPort01], 5, [5], 1>;
|
||||
|
||||
defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFAddX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFAddY, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFAdd64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFAdd64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
|
||||
defm : AtomWriteResPair<WriteFAdd64Y, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
|
||||
defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFCmpX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFCmpY, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFCmp64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFCmp64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
|
||||
defm : AtomWriteResPair<WriteFCmp64Y, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
|
||||
defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
|
||||
defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFMulY, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
|
||||
defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
|
||||
defm : AtomWriteResPair<WriteFMul64X, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
|
||||
defm : AtomWriteResPair<WriteFMul64Y, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
|
||||
defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
|
||||
defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
|
||||
defm : AtomWriteResPair<WriteFRcpY, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
|
||||
@ -398,8 +410,7 @@ def AtomWrite0_5 : SchedWriteRes<[AtomPort0]> {
|
||||
let Latency = 5;
|
||||
let ResourceCycles = [5];
|
||||
}
|
||||
def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)",
|
||||
"MUL(PS|SD)(rr|rm)(_Int)?")>;
|
||||
def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)")>;
|
||||
|
||||
// Port1
|
||||
def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
|
||||
@ -518,13 +529,10 @@ def : InstRW<[AtomWrite01_6], (instrs LD_F1, CMPXCHG8rm, INTO, XLAT,
|
||||
SHLD16rri8, SHRD16rri8,
|
||||
SHLD16mrCL, SHRD16mrCL,
|
||||
SHLD16mri8, SHRD16mri8,
|
||||
ADDSUBPDrr, ADDSUBPDrm,
|
||||
CVTPS2DQrr, CVTTPS2DQrr)>;
|
||||
def : InstRW<[AtomWrite01_6], (instregex "IMUL16rr",
|
||||
"IST_F(P)?(16|32|64)?m",
|
||||
"MMX_PH(ADD|SUB)S?Wrm",
|
||||
"(ADD|SUB|MAX|MIN)PDrr",
|
||||
"CMPPDrri")>;
|
||||
"MMX_PH(ADD|SUB)S?Wrm")>;
|
||||
|
||||
def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
|
||||
let Latency = 7;
|
||||
@ -541,8 +549,6 @@ def : InstRW<[AtomWrite01_7], (instrs AAD8i8,
|
||||
MMX_CVTPD2PIirr,
|
||||
MMX_CVTPI2PDirr,
|
||||
MMX_CVTTPD2PIirr)>;
|
||||
def : InstRW<[AtomWrite01_7], (instregex "(ADD|SUB|MAX|MIN)PDrm",
|
||||
"CMPPDrmi")>;
|
||||
|
||||
def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
|
||||
let Latency = 8;
|
||||
@ -571,8 +577,7 @@ def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr,
|
||||
SHLD64mrCL, SHRD64mrCL,
|
||||
SHLD64mri8, SHRD64mri8,
|
||||
SHLD64rri8, SHRD64rri8,
|
||||
CMPXCHG8rr,
|
||||
MULPDrr)>;
|
||||
CMPXCHG8rr)>;
|
||||
def : InstRW<[AtomWrite01_9], (instregex "CMOV(B|BE|E|P|NB|NBE|NE|NP)_F",
|
||||
"(U)?COM_FI", "TST_F",
|
||||
"(U)?COMIS(D|S)rr",
|
||||
@ -582,8 +587,7 @@ def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
|
||||
let Latency = 10;
|
||||
let ResourceCycles = [10];
|
||||
}
|
||||
def : InstRW<[AtomWrite01_10], (instrs FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI,
|
||||
MULPDrm)>;
|
||||
def : InstRW<[AtomWrite01_10], (instrs FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI)>;
|
||||
def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm",
|
||||
"CVT(T)?SS2SI64rm(_Int)?")>;
|
||||
|
||||
|
||||
@ -317,12 +317,24 @@ def : WriteRes<WriteFMove, [JFPU01, JFPX]>;
|
||||
def : WriteRes<WriteEMMS, [JFPU01, JFPX]> { let Latency = 2; }
|
||||
|
||||
defm : JWriteResFpuPair<WriteFAdd, [JFPU0, JFPA], 3>;
|
||||
defm : JWriteResFpuPair<WriteFAddX, [JFPU0, JFPA], 3>;
|
||||
defm : JWriteResYMMPair<WriteFAddY, [JFPU0, JFPA], 3, [2,2], 2>;
|
||||
defm : JWriteResFpuPair<WriteFAdd64, [JFPU0, JFPA], 3>;
|
||||
defm : JWriteResFpuPair<WriteFAdd64X, [JFPU0, JFPA], 3>;
|
||||
defm : JWriteResYMMPair<WriteFAdd64Y, [JFPU0, JFPA], 3, [2,2], 2>;
|
||||
defm : JWriteResFpuPair<WriteFCmp, [JFPU0, JFPA], 2>;
|
||||
defm : JWriteResFpuPair<WriteFCmpX, [JFPU0, JFPA], 2>;
|
||||
defm : JWriteResYMMPair<WriteFCmpY, [JFPU0, JFPA], 2, [2,2], 2>;
|
||||
defm : JWriteResFpuPair<WriteFCmp64, [JFPU0, JFPA], 2>;
|
||||
defm : JWriteResFpuPair<WriteFCmp64X, [JFPU0, JFPA], 2>;
|
||||
defm : JWriteResYMMPair<WriteFCmp64Y, [JFPU0, JFPA], 2, [2,2], 2>;
|
||||
defm : JWriteResFpuPair<WriteFCom, [JFPU0, JFPA, JALU0], 3>;
|
||||
defm : JWriteResFpuPair<WriteFMul, [JFPU1, JFPM], 2>;
|
||||
defm : JWriteResFpuPair<WriteFMulX, [JFPU1, JFPM], 2>;
|
||||
defm : JWriteResYMMPair<WriteFMulY, [JFPU1, JFPM], 2, [2,2], 2>;
|
||||
defm : JWriteResFpuPair<WriteFMul64, [JFPU1, JFPM], 4, [1,2]>;
|
||||
defm : JWriteResFpuPair<WriteFMul64X, [JFPU1, JFPM], 4, [1,2]>;
|
||||
defm : JWriteResYMMPair<WriteFMul64Y, [JFPU1, JFPM], 4, [2,4], 2>;
|
||||
defm : JWriteResFpuPair<WriteFMA, [JFPU1, JFPM], 2>; // NOTE: Doesn't exist on Jaguar.
|
||||
defm : JWriteResFpuPair<WriteFMAX, [JFPU1, JFPM], 2>; // NOTE: Doesn't exist on Jaguar.
|
||||
defm : JWriteResFpuPair<WriteFMAY, [JFPU1, JFPM], 2>; // NOTE: Doesn't exist on Jaguar.
|
||||
@ -552,32 +564,6 @@ def : InstRW<[JWriteCVTPH2PSYLd], (instrs VCVTPH2PSYrm)>;
|
||||
// AVX instructions.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
def JWriteVMULYPD: SchedWriteRes<[JFPU1, JFPM]> {
|
||||
let Latency = 4;
|
||||
let ResourceCycles = [2, 4];
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def : InstRW<[JWriteVMULYPD], (instrs VMULPDYrr)>;
|
||||
|
||||
def JWriteVMULYPDLd: SchedWriteRes<[JLAGU, JFPU1, JFPM]> {
|
||||
let Latency = 9;
|
||||
let ResourceCycles = [2, 2, 4];
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def : InstRW<[JWriteVMULYPDLd, ReadAfterLd], (instrs VMULPDYrm)>;
|
||||
|
||||
def JWriteVMULPD: SchedWriteRes<[JFPU1, JFPM]> {
|
||||
let Latency = 4;
|
||||
let ResourceCycles = [1, 2];
|
||||
}
|
||||
def : InstRW<[JWriteVMULPD], (instrs MULPDrr, MULSDrr, VMULPDrr, VMULSDrr)>;
|
||||
|
||||
def JWriteVMULPDLd: SchedWriteRes<[JLAGU, JFPU1, JFPM]> {
|
||||
let Latency = 9;
|
||||
let ResourceCycles = [1, 1, 2];
|
||||
}
|
||||
def : InstRW<[JWriteVMULPDLd], (instrs MULPDrm, MULSDrm, VMULPDrm, VMULSDrm)>;
|
||||
|
||||
def JWriteVCVTY: SchedWriteRes<[JFPU1, JSTC]> {
|
||||
let Latency = 3;
|
||||
let ResourceCycles = [2, 2];
|
||||
|
||||
@ -130,13 +130,25 @@ def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
|
||||
def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;
|
||||
defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>;
|
||||
|
||||
defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;
|
||||
defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
|
||||
defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>;
|
||||
defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
|
||||
defm : SLMWriteResPair<WriteFDivY, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
|
||||
|
||||
@ -193,9 +193,17 @@ def : WriteRes<WriteFMove, [ZnFPU]>;
|
||||
def : WriteRes<WriteFLoad, [ZnAGU]> { let Latency = 8; }
|
||||
|
||||
defm : ZnWriteResFpuPair<WriteFAdd, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFAddX, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFAddY, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFAdd64, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFAdd64X, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFAdd64Y, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCmp, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCmpX, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCmpY, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCmp64, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCmp64X, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCmp64Y, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFCom, [ZnFPU0], 3>;
|
||||
defm : ZnWriteResFpuPair<WriteFBlend, [ZnFPU01], 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFBlendY, [ZnFPU01], 1>;
|
||||
@ -224,7 +232,11 @@ defm : ZnWriteResFpuPair<WriteFShuffleY, [ZnFPU12], 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFVarShuffle, [ZnFPU12], 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFVarShuffleY,[ZnFPU12], 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU01], 3, [1], 1, 7, 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMulX, [ZnFPU01], 3, [1], 1, 7, 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMulY, [ZnFPU01], 4, [1], 1, 7, 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMul64, [ZnFPU01], 3, [1], 1, 7, 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMul64X, [ZnFPU01], 3, [1], 1, 7, 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMul64Y, [ZnFPU01], 4, [1], 1, 7, 1>;
|
||||
defm : ZnWriteResFpuPair<WriteFMA, [ZnFPU03], 5>;
|
||||
defm : ZnWriteResFpuPair<WriteFMAX, [ZnFPU03], 5>;
|
||||
defm : ZnWriteResFpuPair<WriteFMAY, [ZnFPU03], 5>;
|
||||
|
||||
@ -29,7 +29,7 @@ define <2 x double> @test_addsubpd(<2 x double> %a0, <2 x double> %a1, <2 x doub
|
||||
; ATOM-LABEL: test_addsubpd:
|
||||
; ATOM: # %bb.0:
|
||||
; ATOM-NEXT: addsubpd %xmm1, %xmm0 # sched: [6:3.00]
|
||||
; ATOM-NEXT: addsubpd (%rdi), %xmm0 # sched: [6:3.00]
|
||||
; ATOM-NEXT: addsubpd (%rdi), %xmm0 # sched: [7:3.50]
|
||||
; ATOM-NEXT: retq # sched: [79:39.50]
|
||||
;
|
||||
; SLM-LABEL: test_addsubpd:
|
||||
|
||||
@ -407,7 +407,7 @@ xorpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 5 5.00 addsd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 1 5 5.00 * addsd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 6 3.00 addsubpd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 1 6 3.00 * addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 7 3.50 * addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 1 0.50 andnpd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 1 1 1.00 * andnpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 1 0.50 andpd %xmm0, %xmm2
|
||||
@ -673,7 +673,7 @@ xorpd (%rax), %xmm2
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1]
|
||||
# CHECK-NEXT: 872.50 644.50
|
||||
# CHECK-NEXT: 873.00 645.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] Instructions:
|
||||
@ -682,7 +682,7 @@ xorpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 5.00 - addsd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 5.00 - addsd (%rax), %xmm2
|
||||
# CHECK-NEXT: 3.00 3.00 addsubpd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 3.00 3.00 addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 3.50 3.50 addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 andnpd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 1.00 - andnpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 andpd %xmm0, %xmm2
|
||||
|
||||
@ -40,7 +40,7 @@ movsldup (%rax), %xmm2
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 1 6 3.00 addsubpd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 1 6 3.00 * addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 7 3.50 * addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 5 5.00 addsubps %xmm0, %xmm2
|
||||
# CHECK-NEXT: 1 5 5.00 * addsubps (%rax), %xmm2
|
||||
# CHECK-NEXT: 1 8 4.00 haddpd %xmm0, %xmm2
|
||||
@ -65,12 +65,12 @@ movsldup (%rax), %xmm2
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1]
|
||||
# CHECK-NEXT: 57.50 41.50
|
||||
# CHECK-NEXT: 58.00 42.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] Instructions:
|
||||
# CHECK-NEXT: 3.00 3.00 addsubpd %xmm0, %xmm2
|
||||
# CHECK-NEXT: 3.00 3.00 addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 3.50 3.50 addsubpd (%rax), %xmm2
|
||||
# CHECK-NEXT: 5.00 - addsubps %xmm0, %xmm2
|
||||
# CHECK-NEXT: 5.00 - addsubps (%rax), %xmm2
|
||||
# CHECK-NEXT: 4.00 4.00 haddpd %xmm0, %xmm2
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user