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Support shr long/ulong.
llvm-svn: 18173
This commit is contained in:
Brian Gaeke
parent
29093f7ec7
commit
ce245ef743
@ -1119,58 +1119,124 @@ void V8ISel::emitShift64 (MachineBasicBlock *MBB,
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bool isSigned = I.getType()->isSigned();
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switch (I.getOpcode ()) {
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case Instruction::Shr: {
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unsigned CarryReg = makeAnotherReg (Type::IntTy),
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ThirtyTwo = makeAnotherReg (Type::IntTy),
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HalfShiftReg = makeAnotherReg (Type::IntTy),
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NegHalfShiftReg = makeAnotherReg (Type::IntTy),
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TempReg = makeAnotherReg (Type::IntTy);
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unsigned OneShiftOutReg = makeAnotherReg (Type::ULongTy),
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TwoShiftsOutReg = makeAnotherReg (Type::ULongTy);
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock ();
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MachineBasicBlock *shiftMBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (shiftMBB);
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MachineBasicBlock *oneShiftMBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (oneShiftMBB);
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MachineBasicBlock *twoShiftsMBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (twoShiftsMBB);
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MachineBasicBlock *continueMBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (continueMBB);
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// .lshr_begin:
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// ...
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// subcc %g0, ShiftAmtReg, %g0 ! Is ShAmt == 0?
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// be .lshr_continue ! Then don't shift.
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// ba .lshr_shift ! else shift.
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BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0)
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.addReg (ShiftAmtReg);
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BuildMI (BB, V8::BE, 1).addMBB (continueMBB);
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BuildMI (BB, V8::BA, 1).addMBB (shiftMBB);
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// Update machine-CFG edges
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BB->addSuccessor (continueMBB);
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BB->addSuccessor (shiftMBB);
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// .lshr_shift: ! [preds: begin]
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// or %g0, 32, ThirtyTwo
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// subcc ThirtyTwo, ShiftAmtReg, HalfShiftReg ! Calculate 32 - shamt
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// bg .lshr_two_shifts ! If >0, b two_shifts
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// ba .lshr_one_shift ! else one_shift.
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BB = shiftMBB;
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BuildMI (BB, V8::ORri, 2, ThirtyTwo).addReg (V8::G0).addSImm (32);
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BuildMI (BB, V8::SUBCCrr, 2, HalfShiftReg).addReg (ThirtyTwo)
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.addReg (ShiftAmtReg);
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BuildMI (BB, V8::BG, 1).addMBB (twoShiftsMBB);
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BuildMI (BB, V8::BA, 1).addMBB (oneShiftMBB);
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// Update machine-CFG edges
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BB->addSuccessor (twoShiftsMBB);
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BB->addSuccessor (oneShiftMBB);
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// .lshr_two_shifts: ! [preds: shift]
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// sll SrcReg, HalfShiftReg, CarryReg ! Save the borrows
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// ! <SHIFT> in following is sra if signed, srl if unsigned
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// <SHIFT> SrcReg, ShiftAmtReg, TwoShiftsOutReg ! Shift top half
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// srl SrcReg+1, ShiftAmtReg, TempReg ! Shift bottom half
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// or TempReg, CarryReg, TwoShiftsOutReg+1 ! Restore the borrows
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// ba .lshr_continue
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unsigned ShiftOpcode = (isSigned ? V8::SRArr : V8::SRLrr);
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BB = twoShiftsMBB;
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BuildMI (BB, V8::SLLrr, 2, CarryReg).addReg (SrcReg)
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.addReg (HalfShiftReg);
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BuildMI (BB, ShiftOpcode, 2, TwoShiftsOutReg).addReg (SrcReg)
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.addReg (ShiftAmtReg);
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BuildMI (BB, V8::SRLrr, 2, TempReg).addReg (SrcReg+1)
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.addReg (ShiftAmtReg);
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BuildMI (BB, V8::ORrr, 2, TwoShiftsOutReg+1).addReg (TempReg)
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.addReg (CarryReg);
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BuildMI (BB, V8::BA, 1).addMBB (continueMBB);
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// Update machine-CFG edges
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BB->addSuccessor (continueMBB);
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// .lshr_one_shift: ! [preds: shift]
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// ! if unsigned:
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// or %g0, %g0, OneShiftOutReg ! Zero top half
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// ! or, if signed:
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// sra SrcReg, 31, OneShiftOutReg ! Sign-ext top half
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// sub %g0, HalfShiftReg, NegHalfShiftReg ! Make ShiftAmt >0
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// <SHIFT> SrcReg, NegHalfShiftReg, OneShiftOutReg+1 ! Shift bottom half
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// ba .lshr_continue
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BB = oneShiftMBB;
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if (isSigned)
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BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
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else
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BuildMI (BB, V8::ORrr, 2, OneShiftOutReg).addReg (V8::G0)
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.addReg (V8::G0);
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BuildMI (BB, V8::SUBrr, 2, NegHalfShiftReg).addReg (V8::G0)
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.addReg (HalfShiftReg);
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BuildMI (BB, ShiftOpcode, 2, OneShiftOutReg+1).addReg (SrcReg)
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.addReg (NegHalfShiftReg);
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BuildMI (BB, V8::BA, 1).addMBB (continueMBB);
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// Update machine-CFG edges
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BB->addSuccessor (continueMBB);
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// .lshr_continue: ! [preds: begin, do_one_shift, do_two_shifts]
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// phi (SrcReg, begin), (TwoShiftsOutReg, two_shifts),
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// (OneShiftOutReg, one_shift), DestReg ! Phi top half...
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// phi (SrcReg+1, begin), (TwoShiftsOutReg+1, two_shifts),
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// (OneShiftOutReg+1, one_shift), DestReg+1 ! And phi bottom half.
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BB = continueMBB;
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BuildMI (BB, V8::PHI, 6, DestReg).addReg (SrcReg).addMBB (thisMBB)
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.addReg (TwoShiftsOutReg).addMBB (twoShiftsMBB)
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.addReg (OneShiftOutReg).addMBB (oneShiftMBB);
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BuildMI (BB, V8::PHI, 6, DestReg+1).addReg (SrcReg+1).addMBB (thisMBB)
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.addReg (TwoShiftsOutReg+1).addMBB (twoShiftsMBB)
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.addReg (OneShiftOutReg+1).addMBB (oneShiftMBB);
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return;
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}
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case Instruction::Shl:
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case Instruction::Shr:
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if (!isSigned) {
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unsigned CarryReg = makeAnotherReg (Type::IntTy),
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ThirtyTwo = makeAnotherReg (Type::IntTy),
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HalfShiftReg = makeAnotherReg (Type::IntTy),
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NegHalfShiftReg = makeAnotherReg (Type::IntTy),
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TempReg = makeAnotherReg (Type::IntTy);
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unsigned OneShiftOutReg = makeAnotherReg (Type::ULongTy),
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TwoShiftsOutReg = makeAnotherReg (Type::ULongTy);
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/*
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.lshr_begin:
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...
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// Check whether the shift amount is zero:
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V8::G0 = V8::SUBCCrr V8::G0, ShiftAmountReg
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V8::BE .lshr_continue
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V8::BA .lshr_shift
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.lshr_shift: // [preds: begin]
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// Calculate 32 - shamt:
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ThirtyTwo = V8::ORri V8::G0, 32
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HalfShiftReg = V8::SUBCCrr ThirtyTwo, ShiftAmountReg
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// See whether it was greater than 0:
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V8::BG .lshr_two_shifts
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V8::BA .lshr_one_shift
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.lshr_two_shifts: // [preds: shift]
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CarryReg = V8::SLLrr SrcReg, HalfShiftReg
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TwoShiftsOutReg = V8::SRLrr SrcReg, ShiftAmountReg
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TempReg = V8::SRLrr SrcReg+1, ShiftAmountReg
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TwoShiftsOutReg+1 = V8::ORrr TempReg, CarryReg
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V8::BA .lshr_continue
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.lshr_one_shift: // [preds: shift]
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OneShiftOutReg = V8::ORrr V8::G0, V8::G0
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NegHalfShiftReg = V8::SUBrr V8::G0, HalfShiftReg
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OneShiftOutReg+1 = V8::SRLrr SrcReg, NegHalfShiftReg
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V8::BA .lshr_continue
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.lshr_continue: // [preds: begin, do_one_shift, do_two_shifts]
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DestReg = V8::PHI (SrcReg, begin), (TwoShiftsOutReg, two_shifts),
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(OneShiftOutReg, one_shift)
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DestReg+1 = V8::PHI (SrcReg+1, begin), (TwoShiftsOutReg+1, two_shifts),
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(OneShiftOutReg+1, one_shift)
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...
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*/
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std::cerr << "Sorry, 64-bit lshr is not yet supported:\n" << I;
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abort ();
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return;
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}
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default:
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std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
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abort ();
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