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Use the cached subtarget off of the machine function.

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llvm-svn: 232782
This commit is contained in:
Eric Christopher 2015-03-19 23:06:21 +00:00
parent 2dc56fc992
commit ce4aca045f
2 changed files with 8 additions and 9 deletions
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2
include/llvm/Target/TargetInstrInfo.h
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@ -207,7 +207,7 @@ public:
/// this, particularly to support spilled vector registers. /// this, particularly to support spilled vector registers.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
unsigned &Size, unsigned &Offset, unsigned &Size, unsigned &Offset,
const TargetMachine *TM) const; const MachineFunction &MF) const;
/// isAsCheapAsAMove - Return true if the instruction is as cheap as a move /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move
/// instruction. /// instruction.

15
lib/CodeGen/TargetInstrInfo.cpp
View File

@ -285,21 +285,20 @@ bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
unsigned SubIdx, unsigned &Size, unsigned SubIdx, unsigned &Size,
unsigned &Offset, unsigned &Offset,
const TargetMachine *TM) const { const MachineFunction &MF) const {
if (!SubIdx) { if (!SubIdx) {
Size = RC->getSize(); Size = RC->getSize();
Offset = 0; Offset = 0;
return true; return true;
} }
unsigned BitSize = const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxSize(SubIdx); unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
// Convert bit size to byte size to be consistent with // Convert bit size to byte size to be consistent with
// MCRegisterClass::getSize(). // MCRegisterClass::getSize().
if (BitSize % 8) if (BitSize % 8)
return false; return false;
int BitOffset = int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxOffset(SubIdx);
if (BitOffset < 0 || BitOffset % 8) if (BitOffset < 0 || BitOffset % 8)
return false; return false;
@ -308,7 +307,7 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
assert(RC->getSize() >= (Offset + Size) && "bad subregister range"); assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
if (!TM->getDataLayout()->isLittleEndian()) { if (!MF.getTarget().getDataLayout()->isLittleEndian()) {
Offset = RC->getSize() - (Offset + Size); Offset = RC->getSize() - (Offset + Size);
} }
return true; return true;
@ -423,8 +422,8 @@ static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr *MI,
// Compute the spill slot size and offset. // Compute the spill slot size and offset.
const TargetRegisterClass *RC = const TargetRegisterClass *RC =
MF.getRegInfo().getRegClass(MO.getReg()); MF.getRegInfo().getRegClass(MO.getReg());
bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, bool Valid =
SpillOffset, &MF.getTarget()); TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
if (!Valid) if (!Valid)
report_fatal_error("cannot spill patchpoint subregister operand"); report_fatal_error("cannot spill patchpoint subregister operand");
MIB.addImm(StackMaps::IndirectMemRefOp); MIB.addImm(StackMaps::IndirectMemRefOp);