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[Hexagon] Adding double-logic on predicate instructions.

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llvm-svn: 225018
This commit is contained in:
Colin LeMahieu 2014-12-30 23:22:39 +00:00
parent ca09b563e4
commit ce5a9848a5
2 changed files with 82 additions and 2 deletions
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60
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -1573,6 +1573,66 @@ def J4_hintjumpr: JRInst <
// NV/J -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// CR +
//===----------------------------------------------------------------------===//
// PC-relative add
let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
Uses = [PC], validSubTargets = HasV4SubT in
def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
"$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
bits<5> Rd;
bits<6> u6;
let IClass = 0b0110;
let Inst{27-16} = 0b101001001001;
let Inst{12-7} = u6;
let Inst{4-0} = Rd;
}
let hasSideEffects = 0 in
class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
: CRInst<(outs PredRegs:$Pd),
(ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
"$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
!if (IsNeg,"!","") # "$Pu))",
[], "", CR_tc_2early_SLOT23> {
bits<2> Pd;
bits<2> Ps;
bits<2> Pt;
bits<2> Pu;
let IClass = 0b0110;
let Inst{27-24} = 0b1011;
let Inst{23} = IsNeg;
let Inst{22-21} = OpBits;
let Inst{20} = 0b1;
let Inst{17-16} = Ps;
let Inst{13} = 0b0;
let Inst{9-8} = Pt;
let Inst{7-6} = Pu;
let Inst{1-0} = Pd;
}
let isCodeGenOnly = 0 in {
def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
}
//===----------------------------------------------------------------------===//
// CR -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// XTYPE/ALU +
//===----------------------------------------------------------------------===//

24
test/MC/Disassembler/Hexagon/cr.txt
View File

@ -26,16 +26,36 @@
# CHECK: p3 = sp3loop0
0x01 0xc3 0x02 0x6b
# CHECK: p1 = and(p3, p2)
0xc1 0xc3 0x12 0x6b
# CHECK: p1 = and(p2, and(p3, p3))
0x01 0xc3 0x62 0x6b
# CHECK: p1 = and(p3, !p2)
0x01 0xc3 0x22 0x6b
# CHECK: p1 = or(p3, p2)
0xc1 0xc3 0x32 0x6b
# CHECK: p1 = and(p2, or(p3, p3))
0x01 0xc3 0xe2 0x6b
# CHECK: p1 = or(p3, !p2)
0x01 0xc0 0xc2 0x6b
# CHECK: p1 = not(p2)
0x01 0xc2 0x43 0x6b
# CHECK: p1 = xor(p3, p2)
0xc1 0xc3 0x52 0x6b
# CHECK: p1 = or(p2, and(p3, p3))
0x01 0xc2 0x63 0x6b
# CHECK: p1 = and(p2, !p3)
0xc1 0xc3 0x72 0x6b
# CHECK: p1 = or(p2, or(p3, p3))
0xc1 0xc3 0x92 0x6b
# CHECK: p1 = and(p2, and(p3, !p3))
0xc1 0xc3 0xb2 0x6b
# CHECK: p1 = and(p2, or(p3, !p3))
0x01 0xc0 0xc2 0x6b
# CHECK: p1 = not(p2)
0xc1 0xc3 0xd2 0x6b
# CHECK: p1 = or(p2, and(p3, !p3))
0x01 0xc2 0xe3 0x6b
# CHECK: p1 = or(p2, !p3)
0xc1 0xc3 0xf2 0x6b
# CHECK: p1 = or(p2, or(p3, !p3))
0x0d 0xc0 0x35 0x62
# CHECK: cs1 = r21
0x11 0xc0 0x0d 0x6a