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https://github.com/RPCS3/llvm-mirror.git
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- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
llvm-svn: 128585
This commit is contained in:
Bruno Cardoso Lopes
parent
1b8f91d2c8
commit
cebbf7fe68
@ -200,6 +200,51 @@ inline static unsigned getARMRegisterNumbering(unsigned Reg) {
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}
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namespace ARMII {
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/// ARM Addressing Modes
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enum AddrMode {
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AddrModeNone = 0,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrMode6 = 6,
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AddrModeT1_1 = 7,
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AddrModeT1_2 = 8,
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AddrModeT1_4 = 9,
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AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
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AddrModeT2_i12 = 11,
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AddrModeT2_i8 = 12,
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AddrModeT2_so = 13,
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AddrModeT2_pc = 14, // +/- i12 for pc relative data
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AddrModeT2_i8s4 = 15, // i8 * 4
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AddrMode_i12 = 16
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};
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inline static const char *AddrModeToString(AddrMode addrmode) {
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switch (addrmode) {
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default: llvm_unreachable("Unknown memory operation");
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case AddrModeNone: return "AddrModeNone";
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case AddrMode1: return "AddrMode1";
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case AddrMode2: return "AddrMode2";
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case AddrMode3: return "AddrMode3";
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case AddrMode4: return "AddrMode4";
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case AddrMode5: return "AddrMode5";
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case AddrMode6: return "AddrMode6";
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case AddrModeT1_1: return "AddrModeT1_1";
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case AddrModeT1_2: return "AddrModeT1_2";
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case AddrModeT1_4: return "AddrModeT1_4";
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case AddrModeT1_s: return "AddrModeT1_s";
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case AddrModeT2_i12: return "AddrModeT2_i12";
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case AddrModeT2_i8: return "AddrModeT2_i8";
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case AddrModeT2_so: return "AddrModeT2_so";
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case AddrModeT2_pc: return "AddrModeT2_pc";
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case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
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case AddrMode_i12: return "AddrMode_i12";
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}
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}
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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@ -34,25 +34,7 @@ namespace ARMII {
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//===------------------------------------------------------------------===//
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// This four-bit field describes the addressing mode used.
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AddrModeMask = 0x1f,
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AddrModeNone = 0,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrMode6 = 6,
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AddrModeT1_1 = 7,
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AddrModeT1_2 = 8,
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AddrModeT1_4 = 9,
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AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
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AddrModeT2_i12 = 11,
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AddrModeT2_i8 = 12,
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AddrModeT2_so = 13,
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AddrModeT2_pc = 14, // +/- i12 for pc relative data
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AddrModeT2_i8s4 = 15, // i8 * 4
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AddrMode_i12 = 16,
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AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
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// Size* - Flags to keep track of the size of an instruction.
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SizeShift = 5,
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@ -515,15 +515,15 @@ class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
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: AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
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pattern> {
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// AM2 store w/ two operands: (GPR, am2offset)
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// {17-14} Rn
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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bits<18> addr;
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let Inst{25} = addr{13};
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let Inst{23} = addr{12};
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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}
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// addrmode3 instructions
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@ -498,6 +498,12 @@ def ldst_so_reg : Operand<i32>,
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def MemMode2AsmOperand : AsmOperandClass {
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let Name = "MemMode2";
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let SuperClasses = [];
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let ParserMethod = "tryParseMemMode2Operand";
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}
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// addrmode2 := reg +/- imm12
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// := reg +/- reg shop imm
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//
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@ -505,6 +511,7 @@ def addrmode2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode2", []> {
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let EncoderMethod = "getAddrMode2OpValue";
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let PrintMethod = "printAddrMode2Operand";
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let ParserMatchClass = MemMode2AsmOperand;
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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@ -1656,6 +1663,7 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
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let Inst{23} = addr{12};
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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}
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def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset),
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@ -1714,17 +1722,35 @@ defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
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// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
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let mayLoad = 1, neverHasSideEffects = 1 in {
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def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am2offset:$offset), IndexModePost,
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LdFrm, IIC_iLoad_ru,
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"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
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"ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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// {17-14} Rn
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<18> addr;
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let Inst{25} = addr{13};
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let Inst{23} = addr{12};
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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}
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def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am2offset:$offset), IndexModePost,
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LdFrm, IIC_iLoad_bh_ru,
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"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
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"ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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// {17-14} Rn
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<18> addr;
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let Inst{25} = addr{13};
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let Inst{23} = addr{12};
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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}
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def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am3offset:$offset), IndexModePost,
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@ -1818,20 +1844,20 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
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// STRT, STRBT, and STRHT are for disassembly only.
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def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
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def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
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IndexModePost, StFrm, IIC_iStore_ru,
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"strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
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"strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
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}
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def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
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def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
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IndexModePost, StFrm, IIC_iStore_bh_ru,
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"strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
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"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
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}
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def STRHT: AI3sthpo<(outs GPR:$base_wb),
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@ -3391,8 +3417,9 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{23-20} = opc1;
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}
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class ACI<dag oops, dag iops, string opc, string asm>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
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class ACI<dag oops, dag iops, string opc, string asm,
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IndexMode im = IndexModeNone>
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: I<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
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opc, asm, "", [/* For disassembly only; pattern left blank */]> {
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let Inst{27-25} = 0b110;
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}
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@ -3411,7 +3438,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
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def _PRE : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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opc, "\tp$cop, cr$CRd, $addr!"> {
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opc, "\tp$cop, cr$CRd, $addr!", IndexModePre> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 1; // W = 1
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@ -3452,7 +3479,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
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def L_PRE : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
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!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 1; // W = 1
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@ -48,7 +48,8 @@ class ARMAsmParser : public TargetAsmParser {
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bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
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ARMII::AddrMode AddrMode);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
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bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
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const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
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@ -95,6 +96,14 @@ class ARMAsmParser : public TargetAsmParser {
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy tryParseMSRMaskOperand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy tryParseMemMode2Operand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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// Asm Match Converter Methods
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bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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public:
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ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
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@ -172,6 +181,7 @@ class ARMOperand : public MCParsedAsmOperand {
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/// Combined record for all forms of ARM address expressions.
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struct {
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ARMII::AddrMode AddrMode;
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unsigned BaseRegNum;
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union {
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unsigned RegNum; ///< Offset register num, when OffsetIsReg.
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@ -293,7 +303,9 @@ public:
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/// @name Memory Operand Accessors
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/// @{
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ARMII::AddrMode getMemAddrMode() const {
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return Mem.AddrMode;
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}
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unsigned getMemBaseRegNum() const {
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return Mem.BaseRegNum;
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}
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@ -338,6 +350,27 @@ public:
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bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
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bool isMemory() const { return Kind == Memory; }
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bool isShifter() const { return Kind == Shifter; }
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bool isMemMode2() const {
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if (getMemAddrMode() != ARMII::AddrMode2)
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return false;
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if (getMemOffsetIsReg())
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return true;
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if (getMemNegative() &&
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!(getMemPostindexed() || getMemPreindexed()))
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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// The offset must be in the range 0-4095 (imm12).
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if (Value > 4095 || Value < -4095)
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return false;
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return true;
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}
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bool isMemMode5() const {
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if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
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getMemNegative())
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@ -465,6 +498,46 @@ public:
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"No offset operand support in mode 7");
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}
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void addMemMode2Operands(MCInst &Inst, unsigned N) const {
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assert(isMemMode2() && "Invalid mode or number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
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if (getMemOffsetIsReg()) {
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Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
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ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
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ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
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int64_t ShiftAmount = 0;
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if (getMemOffsetRegShifted()) {
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ShOpc = getMemShiftType();
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const MCConstantExpr *CE =
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dyn_cast<MCConstantExpr>(getMemShiftAmount());
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ShiftAmount = CE->getValue();
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}
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
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ShOpc)));
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return;
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}
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// Create a operand placeholder to always yield the same number of operands.
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Inst.addOperand(MCOperand::CreateReg(0));
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// FIXME: #-0 is encoded differently than #0. Does the parser preserve
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// the difference?
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
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assert(CE && "Non-constant mode 2 offset operand!");
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int64_t Offset = CE->getValue();
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if (Offset >= 0)
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
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Offset, ARM_AM::no_shift)));
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else
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
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-Offset, ARM_AM::no_shift)));
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}
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void addMemMode5Operands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && isMemMode5() && "Invalid number of operands!");
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@ -599,9 +672,9 @@ public:
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return Op;
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}
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static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
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const MCExpr *Offset, int OffsetRegNum,
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bool OffsetRegShifted,
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static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
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bool OffsetIsReg, const MCExpr *Offset,
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int OffsetRegNum, bool OffsetRegShifted,
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enum ARM_AM::ShiftOpc ShiftType,
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const MCExpr *ShiftAmount, bool Preindexed,
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bool Postindexed, bool Negative, bool Writeback,
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@ -618,6 +691,7 @@ public:
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"Cannot have expression offset and register offset!");
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ARMOperand *Op = new ARMOperand(Memory);
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Op->Mem.AddrMode = AddrMode;
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Op->Mem.BaseRegNum = BaseRegNum;
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Op->Mem.OffsetIsReg = OffsetIsReg;
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if (OffsetIsReg)
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@ -689,7 +763,8 @@ void ARMOperand::dump(raw_ostream &OS) const {
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break;
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case Memory:
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OS << "<memory "
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<< "base:" << getMemBaseRegNum();
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<< "am:" << ARMII::AddrModeToString(getMemAddrMode())
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<< " base:" << getMemBaseRegNum();
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if (getMemOffsetIsReg()) {
|
||||
OS << " offset:<register " << getMemOffsetRegNum();
|
||||
if (getMemOffsetRegShifted()) {
|
||||
@ -1132,13 +1207,57 @@ tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
return MatchOperand_Success;
|
||||
}
|
||||
|
||||
/// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
|
||||
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
|
||||
tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
SMLoc S = Parser.getTok().getLoc();
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
assert(Tok.is(AsmToken::LBrac) && "Token is not a \"[\"");
|
||||
|
||||
if (ParseMemory(Operands, ARMII::AddrMode2))
|
||||
return MatchOperand_NoMatch;
|
||||
|
||||
return MatchOperand_Success;
|
||||
}
|
||||
|
||||
/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
bool ARMAsmParser::
|
||||
CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
|
||||
((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
return true;
|
||||
}
|
||||
|
||||
/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
bool ARMAsmParser::
|
||||
CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
return true;
|
||||
}
|
||||
|
||||
/// Parse an ARM memory expression, return false if successful else return true
|
||||
/// or an error. The first token must be a '[' when called.
|
||||
///
|
||||
/// TODO Only preindexing and postindexing addressing are started, unindexed
|
||||
/// with option, etc are still to do.
|
||||
bool ARMAsmParser::
|
||||
ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
|
||||
SMLoc S, E;
|
||||
assert(Parser.getTok().is(AsmToken::LBrac) &&
|
||||
"Token is not a Left Bracket");
|
||||
@ -1231,11 +1350,10 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
Offset = MCConstantExpr::Create(0, getContext());
|
||||
}
|
||||
|
||||
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
|
||||
OffsetRegNum, OffsetRegShifted,
|
||||
ShiftType, ShiftAmount, Preindexed,
|
||||
Postindexed, Negative, Writeback,
|
||||
S, E));
|
||||
Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
|
||||
Offset, OffsetRegNum, OffsetRegShifted,
|
||||
ShiftType, ShiftAmount, Preindexed,
|
||||
Postindexed, Negative, Writeback, S, E));
|
||||
if (WBOp)
|
||||
Operands.push_back(WBOp);
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#define DEBUG_TYPE "asm-printer"
|
||||
#include "ARMBaseInfo.h"
|
||||
#include "ARMInstPrinter.h"
|
||||
#include "ARMInstrInfo.h"
|
||||
#include "ARMAddressingModes.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
@ -181,18 +182,12 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(Op);
|
||||
const MCOperand &MO2 = MI->getOperand(Op+1);
|
||||
const MCOperand &MO3 = MI->getOperand(Op+2);
|
||||
|
||||
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
||||
printOperand(MI, Op, O);
|
||||
return;
|
||||
}
|
||||
|
||||
O << "[" << getRegisterName(MO1.getReg());
|
||||
|
||||
if (!MO2.getReg()) {
|
||||
@ -215,6 +210,52 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
|
||||
O << "]";
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(Op);
|
||||
const MCOperand &MO2 = MI->getOperand(Op+1);
|
||||
const MCOperand &MO3 = MI->getOperand(Op+2);
|
||||
|
||||
O << "[" << getRegisterName(MO1.getReg()) << "], ";
|
||||
|
||||
if (!MO2.getReg()) {
|
||||
unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
|
||||
O << '#'
|
||||
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
|
||||
<< ImmOffs;
|
||||
return;
|
||||
}
|
||||
|
||||
O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
|
||||
<< getRegisterName(MO2.getReg());
|
||||
|
||||
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
|
||||
O << ", "
|
||||
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
|
||||
<< " #" << ShImm;
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(Op);
|
||||
|
||||
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
||||
printOperand(MI, Op, O);
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned Opcode = MI->getOpcode();
|
||||
const TargetInstrDesc &Desc = TM.getInstrInfo()->get(Opcode);
|
||||
uint64_t TSFlags = Desc.TSFlags;
|
||||
unsigned IdxMode = (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
|
||||
|
||||
if (IdxMode == ARMII::IndexModePost) {
|
||||
printAM2PostIndexOp(MI, Op, O);
|
||||
return;
|
||||
}
|
||||
printAM2PreOrOffsetIndexOp(MI, Op, O);
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
|
||||
unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
|
||||
@ -22,9 +22,11 @@ class MCOperand;
|
||||
class TargetMachine;
|
||||
|
||||
class ARMInstPrinter : public MCInstPrinter {
|
||||
private:
|
||||
TargetMachine &TM;
|
||||
public:
|
||||
ARMInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
|
||||
: MCInstPrinter(MAI) {}
|
||||
ARMInstPrinter(TargetMachine &_TM, const MCAsmInfo &MAI)
|
||||
: MCInstPrinter(MAI), TM(_TM) {}
|
||||
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &O);
|
||||
virtual StringRef getOpcodeName(unsigned Opcode) const;
|
||||
@ -42,7 +44,11 @@ public:
|
||||
void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
34
test/MC/ARM/arm_addrmode2.s
Normal file
34
test/MC/ARM/arm_addrmode2.s
Normal file
@ -0,0 +1,34 @@
|
||||
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
|
||||
|
||||
@ Post-indexed
|
||||
@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
|
||||
@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
|
||||
@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
|
||||
@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
|
||||
@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
|
||||
@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
|
||||
@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
|
||||
@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
|
||||
@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
|
||||
@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
|
||||
@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
|
||||
@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
|
||||
ldrt r1, [r0], r2
|
||||
ldrt r1, [r0], r2, lsr #3
|
||||
ldrt r1, [r0], #4
|
||||
ldrbt r1, [r0], r2
|
||||
ldrbt r1, [r0], r2, lsr #3
|
||||
ldrbt r1, [r0], #4
|
||||
strt r1, [r0], r2
|
||||
strt r1, [r0], r2, lsr #3
|
||||
strt r1, [r0], #4
|
||||
strbt r1, [r0], r2
|
||||
strbt r1, [r0], r2, lsr #3
|
||||
strbt r1, [r0], #4
|
||||
|
||||
@ Pre-indexed
|
||||
@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
|
||||
@ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
|
||||
ldr r1, [r0, r2, lsr #3]!
|
||||
ldrb r1, [r0, r2, lsr #3]!
|
||||
|
||||
Loading…
Reference in New Issue
Block a user