From cee7bd6b73bc14a1afc0ecab326b986838440c32 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 19 Jan 2012 08:50:38 +0000 Subject: [PATCH] Folding table additions and fixes for AVX. llvm-svn: 148467 --- lib/Target/X86/X86InstrInfo.cpp | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 4f1c798501f..b23801c68e7 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -516,9 +516,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 }, { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 }, { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 }, - { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_16 }, { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 }, - { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_16 }, { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 }, { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 }, { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 }, @@ -535,16 +533,26 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) // AVX 256-bit foldable instructions { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, - { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_16 }, + { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, + { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 }, + { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 }, // AVX2 foldable instructions - { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_16 }, - { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_16 }, - { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_16 }, - { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_16 }, - { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_16 }, - { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_16 } + { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 }, + { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 }, + { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 }, + { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 }, + { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 }, + { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 }, + { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 }, + { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 }, + { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 }, + { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 }, + { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 }, + { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 }, + { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 }, + { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 }, }; for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { @@ -1035,6 +1043,10 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 }, { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 }, { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 }, + { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 }, + { X86::VPERMPDYrr, X86::VPERMPDYrm, TB_ALIGN_32 }, + { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 }, + { X86::VPERMQYrr, X86::VPERMQYrm, TB_ALIGN_32 }, { X86::VPHADDDrr256, X86::VPHADDDrm256, TB_ALIGN_32 }, { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 }, { X86::VPHADDWrr256, X86::VPHADDWrm256, TB_ALIGN_32 },