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[ARM][MIPS] Add funnel shift test coverage
Based on offline discussions regarding D89139 and D88783 - we want to make sure targets aren't doing anything particularly dumb Tests copied from aarch64 which has a mixture of general, legalization and special case tests
This commit is contained in:
Simon Pilgrim
parent
5c60ef51ef
commit
cf6dd3759a
367
test/CodeGen/ARM/funnel-shift-rot.ll
Normal file
367
test/CodeGen/ARM/funnel-shift-rot.ll
Normal file
@ -0,0 +1,367 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 | FileCheck %s --check-prefixes=CHECK,SCALAR
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,NEON
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; When first 2 operands match, it's a rotate.
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define i8 @rotl_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotl_i8_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r1, r0
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; CHECK-NEXT: lsl r0, r0, #3
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; CHECK-NEXT: orr r0, r0, r1, lsr #5
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; CHECK-NEXT: bx lr
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%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i64 @rotl_i64_const_shift(i64 %x) {
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; CHECK-LABEL: rotl_i64_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsl r2, r0, #3
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; CHECK-NEXT: orr r2, r2, r1, lsr #29
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; CHECK-NEXT: lsl r1, r1, #3
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; CHECK-NEXT: orr r1, r1, r0, lsr #29
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
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ret i64 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotl_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotl_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r2, r1, #15
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: and r1, r1, #15
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; CHECK-NEXT: lsl r2, r0, r2
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: orr r0, r2, r0, lsr r1
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; CHECK-NEXT: bx lr
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%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotl_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotl_i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: ror r0, r0, r1
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotl_i64(i64 %x, i64 %z) {
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; SCALAR-LABEL: rotl_i64:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: .save {r4, r5, r11, lr}
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; SCALAR-NEXT: push {r4, r5, r11, lr}
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; SCALAR-NEXT: rsb r3, r2, #0
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; SCALAR-NEXT: and r4, r2, #63
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; SCALAR-NEXT: and lr, r3, #63
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; SCALAR-NEXT: rsb r3, lr, #32
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; SCALAR-NEXT: lsl r2, r0, r4
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; SCALAR-NEXT: lsr r12, r0, lr
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; SCALAR-NEXT: orr r3, r12, r1, lsl r3
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; SCALAR-NEXT: subs r12, lr, #32
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; SCALAR-NEXT: lsrpl r3, r1, r12
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; SCALAR-NEXT: subs r5, r4, #32
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; SCALAR-NEXT: movwpl r2, #0
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; SCALAR-NEXT: cmp r5, #0
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; SCALAR-NEXT: orr r2, r2, r3
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; SCALAR-NEXT: rsb r3, r4, #32
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; SCALAR-NEXT: lsr r3, r0, r3
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; SCALAR-NEXT: orr r3, r3, r1, lsl r4
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; SCALAR-NEXT: lslpl r3, r0, r5
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; SCALAR-NEXT: lsr r0, r1, lr
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; SCALAR-NEXT: cmp r12, #0
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; SCALAR-NEXT: movwpl r0, #0
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; SCALAR-NEXT: orr r1, r3, r0
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; SCALAR-NEXT: mov r0, r2
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; SCALAR-NEXT: pop {r4, r5, r11, pc}
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;
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; NEON-LABEL: rotl_i64:
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; NEON: @ %bb.0:
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; NEON-NEXT: .save {r4, r5, r11, lr}
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; NEON-NEXT: push {r4, r5, r11, lr}
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; NEON-NEXT: and r12, r2, #63
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; NEON-NEXT: rsb r2, r2, #0
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; NEON-NEXT: rsb r3, r12, #32
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; NEON-NEXT: and r4, r2, #63
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; NEON-NEXT: subs lr, r12, #32
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; NEON-NEXT: lsr r3, r0, r3
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; NEON-NEXT: lsr r2, r1, r4
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; NEON-NEXT: orr r3, r3, r1, lsl r12
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; NEON-NEXT: lslpl r3, r0, lr
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; NEON-NEXT: subs r5, r4, #32
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; NEON-NEXT: movwpl r2, #0
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; NEON-NEXT: cmp r5, #0
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; NEON-NEXT: orr r2, r3, r2
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; NEON-NEXT: lsr r3, r0, r4
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; NEON-NEXT: rsb r4, r4, #32
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; NEON-NEXT: lsl r0, r0, r12
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; NEON-NEXT: orr r3, r3, r1, lsl r4
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; NEON-NEXT: lsrpl r3, r1, r5
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; NEON-NEXT: cmp lr, #0
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; NEON-NEXT: movwpl r0, #0
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; NEON-NEXT: mov r1, r2
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; NEON-NEXT: orr r0, r0, r3
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; NEON-NEXT: pop {r4, r5, r11, pc}
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; SCALAR-LABEL: rotl_v4i32:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ldr r12, [sp]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r0, r0, r12
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; SCALAR-NEXT: ldr r12, [sp, #4]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r1, r1, r12
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; SCALAR-NEXT: ldr r12, [sp, #8]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r2, r2, r12
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; SCALAR-NEXT: ldr r12, [sp, #12]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r3, r3, r12
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotl_v4i32:
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; NEON: @ %bb.0:
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; NEON-NEXT: mov r12, sp
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; NEON-NEXT: vld1.64 {d16, d17}, [r12]
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; NEON-NEXT: vmov.i32 q10, #0x1f
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; NEON-NEXT: vneg.s32 q9, q8
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; NEON-NEXT: vmov d23, r2, r3
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; NEON-NEXT: vand q9, q9, q10
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; NEON-NEXT: vand q8, q8, q10
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; NEON-NEXT: vmov d22, r0, r1
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; NEON-NEXT: vneg.s32 q9, q9
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; NEON-NEXT: vshl.u32 q8, q11, q8
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; NEON-NEXT: vshl.u32 q9, q11, q9
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {
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; SCALAR-LABEL: rotl_v4i32_rotl_const_shift:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ror r0, r0, #29
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; SCALAR-NEXT: ror r1, r1, #29
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; SCALAR-NEXT: ror r2, r2, #29
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; SCALAR-NEXT: ror r3, r3, #29
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotl_v4i32_rotl_const_shift:
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; NEON: @ %bb.0:
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; NEON-NEXT: vmov d17, r2, r3
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; NEON-NEXT: vmov d16, r0, r1
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; NEON-NEXT: vshr.u32 q9, q8, #29
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; NEON-NEXT: vshl.i32 q8, q8, #3
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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; Repeat everything for funnel shift right.
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; When first 2 operands match, it's a rotate.
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define i8 @rotr_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotr_i8_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r1, r0
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; CHECK-NEXT: lsr r1, r1, #3
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; CHECK-NEXT: orr r0, r1, r0, lsl #5
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; CHECK-NEXT: bx lr
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%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i32 @rotr_i32_const_shift(i32 %x) {
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; CHECK-LABEL: rotr_i32_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, #3
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
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ret i32 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotr_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotr_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r2, r1, #15
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: and r1, r1, #15
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; CHECK-NEXT: uxth r3, r0
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; CHECK-NEXT: lsr r2, r3, r2
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; CHECK-NEXT: orr r0, r2, r0, lsl r1
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; CHECK-NEXT: bx lr
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%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotr_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotr_i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, r1
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotr_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotr_i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r11, lr}
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: and lr, r2, #63
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; CHECK-NEXT: rsb r2, r2, #0
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; CHECK-NEXT: rsb r3, lr, #32
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; CHECK-NEXT: and r4, r2, #63
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; CHECK-NEXT: lsr r12, r0, lr
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; CHECK-NEXT: orr r3, r12, r1, lsl r3
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; CHECK-NEXT: subs r12, lr, #32
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; CHECK-NEXT: lsl r2, r0, r4
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; CHECK-NEXT: lsrpl r3, r1, r12
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; CHECK-NEXT: subs r5, r4, #32
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; CHECK-NEXT: movwpl r2, #0
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; CHECK-NEXT: cmp r5, #0
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; CHECK-NEXT: orr r2, r3, r2
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; CHECK-NEXT: rsb r3, r4, #32
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; CHECK-NEXT: lsr r3, r0, r3
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; CHECK-NEXT: orr r3, r3, r1, lsl r4
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; CHECK-NEXT: lslpl r3, r0, r5
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; CHECK-NEXT: lsr r0, r1, lr
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwpl r0, #0
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; CHECK-NEXT: orr r1, r0, r3
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: pop {r4, r5, r11, pc}
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; SCALAR-LABEL: rotr_v4i32:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ldr r12, [sp]
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; SCALAR-NEXT: ror r0, r0, r12
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; SCALAR-NEXT: ldr r12, [sp, #4]
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; SCALAR-NEXT: ror r1, r1, r12
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; SCALAR-NEXT: ldr r12, [sp, #8]
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; SCALAR-NEXT: ror r2, r2, r12
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; SCALAR-NEXT: ldr r12, [sp, #12]
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; SCALAR-NEXT: ror r3, r3, r12
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotr_v4i32:
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; NEON: @ %bb.0:
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; NEON-NEXT: mov r12, sp
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; NEON-NEXT: vld1.64 {d16, d17}, [r12]
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; NEON-NEXT: vmov.i32 q9, #0x1f
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; NEON-NEXT: vneg.s32 q10, q8
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; NEON-NEXT: vand q8, q8, q9
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; NEON-NEXT: vmov d23, r2, r3
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; NEON-NEXT: vand q9, q10, q9
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; NEON-NEXT: vneg.s32 q8, q8
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; NEON-NEXT: vmov d22, r0, r1
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; NEON-NEXT: vshl.u32 q9, q11, q9
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; NEON-NEXT: vshl.u32 q8, q11, q8
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
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; SCALAR-LABEL: rotr_v4i32_const_shift:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ror r0, r0, #3
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; SCALAR-NEXT: ror r1, r1, #3
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; SCALAR-NEXT: ror r2, r2, #3
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; SCALAR-NEXT: ror r3, r3, #3
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotr_v4i32_const_shift:
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; NEON: @ %bb.0:
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; NEON-NEXT: vmov d17, r2, r3
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; NEON-NEXT: vmov d16, r0, r1
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; NEON-NEXT: vshl.i32 q9, q8, #29
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; NEON-NEXT: vshr.u32 q8, q8, #3
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
|
||||
}
|
||||
|
||||
define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
|
||||
; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
|
||||
; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
|
||||
; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
398
test/CodeGen/ARM/funnel-shift.ll
Normal file
398
test/CodeGen/ARM/funnel-shift.ll
Normal file
@ -0,0 +1,398 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 | FileCheck %s --check-prefixes=CHECK,SCALAR
|
||||
; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,NEON
|
||||
|
||||
declare i8 @llvm.fshl.i8(i8, i8, i8)
|
||||
declare i16 @llvm.fshl.i16(i16, i16, i16)
|
||||
declare i32 @llvm.fshl.i32(i32, i32, i32)
|
||||
declare i64 @llvm.fshl.i64(i64, i64, i64)
|
||||
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
|
||||
|
||||
declare i8 @llvm.fshr.i8(i8, i8, i8)
|
||||
declare i16 @llvm.fshr.i16(i16, i16, i16)
|
||||
declare i32 @llvm.fshr.i32(i32, i32, i32)
|
||||
declare i64 @llvm.fshr.i64(i64, i64, i64)
|
||||
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
|
||||
|
||||
; General case - all operands can be variables.
|
||||
|
||||
define i16 @fshl_i16(i16 %x, i16 %y, i16 %z) {
|
||||
; CHECK-LABEL: fshl_i16:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: and r2, r2, #15
|
||||
; CHECK-NEXT: mov r3, #31
|
||||
; CHECK-NEXT: lsl r1, r1, #16
|
||||
; CHECK-NEXT: bic r3, r3, r2
|
||||
; CHECK-NEXT: lsl r0, r0, r2
|
||||
; CHECK-NEXT: lsr r1, r1, #1
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr r3
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i16 @llvm.fshl.i16(i16 %x, i16 %y, i16 %z)
|
||||
ret i16 %f
|
||||
}
|
||||
|
||||
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
|
||||
; CHECK-LABEL: fshl_i32:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r3, #31
|
||||
; CHECK-NEXT: lsr r1, r1, #1
|
||||
; CHECK-NEXT: bic r3, r3, r2
|
||||
; CHECK-NEXT: and r2, r2, #31
|
||||
; CHECK-NEXT: lsl r0, r0, r2
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr r3
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Verify that weird types are minimally supported.
|
||||
declare i37 @llvm.fshl.i37(i37, i37, i37)
|
||||
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
|
||||
; CHECK-LABEL: fshl_i37:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
|
||||
; CHECK-NEXT: mov r8, r1
|
||||
; CHECK-NEXT: mov r4, r0
|
||||
; CHECK-NEXT: ldr r0, [sp, #24]
|
||||
; CHECK-NEXT: mov r6, r3
|
||||
; CHECK-NEXT: ldr r1, [sp, #28]
|
||||
; CHECK-NEXT: mov r7, r2
|
||||
; CHECK-NEXT: mov r2, #37
|
||||
; CHECK-NEXT: mov r3, #0
|
||||
; CHECK-NEXT: bl __aeabi_uldivmod
|
||||
; CHECK-NEXT: mov r0, #63
|
||||
; CHECK-NEXT: bic r1, r0, r2
|
||||
; CHECK-NEXT: lsl r0, r6, #27
|
||||
; CHECK-NEXT: lsl r3, r7, #27
|
||||
; CHECK-NEXT: orr r0, r0, r7, lsr #5
|
||||
; CHECK-NEXT: and r2, r2, #63
|
||||
; CHECK-NEXT: lsrs r7, r0, #1
|
||||
; CHECK-NEXT: rrx r0, r3
|
||||
; CHECK-NEXT: rsb r3, r1, #32
|
||||
; CHECK-NEXT: lsr r0, r0, r1
|
||||
; CHECK-NEXT: lsl r6, r4, r2
|
||||
; CHECK-NEXT: orr r0, r0, r7, lsl r3
|
||||
; CHECK-NEXT: subs r3, r1, #32
|
||||
; CHECK-NEXT: lsr r1, r7, r1
|
||||
; CHECK-NEXT: lsrpl r0, r7, r3
|
||||
; CHECK-NEXT: subs r5, r2, #32
|
||||
; CHECK-NEXT: movwpl r6, #0
|
||||
; CHECK-NEXT: orr r0, r6, r0
|
||||
; CHECK-NEXT: rsb r6, r2, #32
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: lsr r6, r4, r6
|
||||
; CHECK-NEXT: orr r2, r6, r8, lsl r2
|
||||
; CHECK-NEXT: lslpl r2, r4, r5
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: movwpl r1, #0
|
||||
; CHECK-NEXT: orr r1, r2, r1
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
|
||||
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
|
||||
ret i37 %f
|
||||
}
|
||||
|
||||
; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
|
||||
|
||||
declare i7 @llvm.fshl.i7(i7, i7, i7)
|
||||
define i7 @fshl_i7_const_fold() {
|
||||
; CHECK-LABEL: fshl_i7_const_fold:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #67
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
|
||||
ret i7 %f
|
||||
}
|
||||
|
||||
define i8 @fshl_i8_const_fold_overshift_1() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #128
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshl_i8_const_fold_overshift_2() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold_overshift_2:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #120
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshl_i8_const_fold_overshift_3() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold_overshift_3:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #0
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshl.i8(i8 0, i8 225, i8 8)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
; With constant shift amount, this is 'extr'.
|
||||
|
||||
define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshl_i32_const_shift:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: lsl r0, r0, #9
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr #23
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Check modulo math on shift amount.
|
||||
|
||||
define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshl_i32_const_overshift:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: lsl r0, r0, #9
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr #23
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; 64-bit should also work.
|
||||
|
||||
define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
|
||||
; CHECK-LABEL: fshl_i64_const_overshift:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: lsr r1, r2, #23
|
||||
; CHECK-NEXT: orr r2, r1, r3, lsl #9
|
||||
; CHECK-NEXT: lsl r0, r0, #9
|
||||
; CHECK-NEXT: orr r1, r0, r3, lsr #23
|
||||
; CHECK-NEXT: mov r0, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; This should work without any node-specific logic.
|
||||
|
||||
define i8 @fshl_i8_const_fold() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #128
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
; Repeat everything for funnel shift right.
|
||||
|
||||
; General case - all operands can be variables.
|
||||
|
||||
define i16 @fshr_i16(i16 %x, i16 %y, i16 %z) {
|
||||
; CHECK-LABEL: fshr_i16:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r3, #1
|
||||
; CHECK-NEXT: lsl r0, r0, #1
|
||||
; CHECK-NEXT: bfi r2, r3, #4, #28
|
||||
; CHECK-NEXT: mov r3, #31
|
||||
; CHECK-NEXT: bic r3, r3, r2
|
||||
; CHECK-NEXT: and r2, r2, #31
|
||||
; CHECK-NEXT: lsl r1, r1, #16
|
||||
; CHECK-NEXT: lsl r0, r0, r3
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr r2
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i16 @llvm.fshr.i16(i16 %x, i16 %y, i16 %z)
|
||||
ret i16 %f
|
||||
}
|
||||
|
||||
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
|
||||
; CHECK-LABEL: fshr_i32:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r3, #31
|
||||
; CHECK-NEXT: lsl r0, r0, #1
|
||||
; CHECK-NEXT: bic r3, r3, r2
|
||||
; CHECK-NEXT: and r2, r2, #31
|
||||
; CHECK-NEXT: lsl r0, r0, r3
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr r2
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Verify that weird types are minimally supported.
|
||||
declare i37 @llvm.fshr.i37(i37, i37, i37)
|
||||
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
|
||||
; CHECK-LABEL: fshr_i37:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
|
||||
; CHECK-NEXT: mov r8, r1
|
||||
; CHECK-NEXT: mov r9, r0
|
||||
; CHECK-NEXT: ldr r0, [sp, #32]
|
||||
; CHECK-NEXT: mov r6, r3
|
||||
; CHECK-NEXT: ldr r1, [sp, #36]
|
||||
; CHECK-NEXT: mov r7, r2
|
||||
; CHECK-NEXT: mov r2, #37
|
||||
; CHECK-NEXT: mov r3, #0
|
||||
; CHECK-NEXT: bl __aeabi_uldivmod
|
||||
; CHECK-NEXT: add r0, r2, #27
|
||||
; CHECK-NEXT: lsl r6, r6, #27
|
||||
; CHECK-NEXT: and r1, r0, #63
|
||||
; CHECK-NEXT: lsl r2, r7, #27
|
||||
; CHECK-NEXT: orr r7, r6, r7, lsr #5
|
||||
; CHECK-NEXT: mov r6, #63
|
||||
; CHECK-NEXT: rsb r3, r1, #32
|
||||
; CHECK-NEXT: lsr r2, r2, r1
|
||||
; CHECK-NEXT: subs r12, r1, #32
|
||||
; CHECK-NEXT: bic r6, r6, r0
|
||||
; CHECK-NEXT: orr r2, r2, r7, lsl r3
|
||||
; CHECK-NEXT: lsl r5, r9, #1
|
||||
; CHECK-NEXT: lsrpl r2, r7, r12
|
||||
; CHECK-NEXT: lsl r0, r5, r6
|
||||
; CHECK-NEXT: subs r4, r6, #32
|
||||
; CHECK-NEXT: lsl r3, r8, #1
|
||||
; CHECK-NEXT: movwpl r0, #0
|
||||
; CHECK-NEXT: orr r3, r3, r9, lsr #31
|
||||
; CHECK-NEXT: orr r0, r0, r2
|
||||
; CHECK-NEXT: rsb r2, r6, #32
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: lsr r1, r7, r1
|
||||
; CHECK-NEXT: lsr r2, r5, r2
|
||||
; CHECK-NEXT: orr r2, r2, r3, lsl r6
|
||||
; CHECK-NEXT: lslpl r2, r5, r4
|
||||
; CHECK-NEXT: cmp r12, #0
|
||||
; CHECK-NEXT: movwpl r1, #0
|
||||
; CHECK-NEXT: orr r1, r2, r1
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
|
||||
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
|
||||
ret i37 %f
|
||||
}
|
||||
|
||||
; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
|
||||
|
||||
declare i7 @llvm.fshr.i7(i7, i7, i7)
|
||||
define i7 @fshr_i7_const_fold() {
|
||||
; CHECK-LABEL: fshr_i7_const_fold:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #31
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
|
||||
ret i7 %f
|
||||
}
|
||||
|
||||
define i8 @fshr_i8_const_fold_overshift_1() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #254
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshr_i8_const_fold_overshift_2() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #225
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshr_i8_const_fold_overshift_3() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #255
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
; With constant shift amount, this is 'extr'.
|
||||
|
||||
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshr_i32_const_shift:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: lsl r0, r0, #23
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr #9
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Check modulo math on shift amount. 41-32=9.
|
||||
|
||||
define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshr_i32_const_overshift:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: lsl r0, r0, #23
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsr #9
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; 64-bit should also work. 105-64 = 41.
|
||||
|
||||
define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
|
||||
; CHECK-LABEL: fshr_i64_const_overshift:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: lsl r2, r0, #23
|
||||
; CHECK-NEXT: lsl r1, r1, #23
|
||||
; CHECK-NEXT: orr r2, r2, r3, lsr #9
|
||||
; CHECK-NEXT: orr r1, r1, r0, lsr #9
|
||||
; CHECK-NEXT: mov r0, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; This should work without any node-specific logic.
|
||||
|
||||
define i8 @fshr_i8_const_fold() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, #254
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshr_i32_shift_by_bitwidth:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: bx lr
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
|
||||
; SCALAR-LABEL: fshr_v4i32_shift_by_bitwidth:
|
||||
; SCALAR: @ %bb.0:
|
||||
; SCALAR-NEXT: ldm sp, {r0, r1, r2, r3}
|
||||
; SCALAR-NEXT: bx lr
|
||||
;
|
||||
; NEON-LABEL: fshr_v4i32_shift_by_bitwidth:
|
||||
; NEON: @ %bb.0:
|
||||
; NEON-NEXT: mov r0, sp
|
||||
; NEON-NEXT: vld1.64 {d16, d17}, [r0]
|
||||
; NEON-NEXT: vmov r0, r1, d16
|
||||
; NEON-NEXT: vmov r2, r3, d17
|
||||
; NEON-NEXT: bx lr
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
415
test/CodeGen/Mips/funnel-shift-rot.ll
Normal file
415
test/CodeGen/Mips/funnel-shift-rot.ll
Normal file
@ -0,0 +1,415 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=mips-linux-gnu -march=mips -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE
|
||||
; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE
|
||||
|
||||
declare i8 @llvm.fshl.i8(i8, i8, i8)
|
||||
declare i16 @llvm.fshl.i16(i16, i16, i16)
|
||||
declare i32 @llvm.fshl.i32(i32, i32, i32)
|
||||
declare i64 @llvm.fshl.i64(i64, i64, i64)
|
||||
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
|
||||
|
||||
declare i8 @llvm.fshr.i8(i8, i8, i8)
|
||||
declare i16 @llvm.fshr.i16(i16, i16, i16)
|
||||
declare i32 @llvm.fshr.i32(i32, i32, i32)
|
||||
declare i64 @llvm.fshr.i64(i64, i64, i64)
|
||||
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
|
||||
|
||||
; When first 2 operands match, it's a rotate.
|
||||
|
||||
define i8 @rotl_i8_const_shift(i8 %x) {
|
||||
; CHECK-LABEL: rotl_i8_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: sll $1, $4, 3
|
||||
; CHECK-NEXT: andi $2, $4, 224
|
||||
; CHECK-NEXT: srl $2, $2, 5
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $1, $2
|
||||
%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i64 @rotl_i64_const_shift(i64 %x) {
|
||||
; CHECK-LABEL: rotl_i64_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: srl $1, $5, 29
|
||||
; CHECK-NEXT: sll $2, $4, 3
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
; CHECK-NEXT: srl $1, $4, 29
|
||||
; CHECK-NEXT: sll $3, $5, 3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $3, $3, $1
|
||||
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; When first 2 operands match, it's a rotate (by variable amount).
|
||||
|
||||
define i16 @rotl_i16(i16 %x, i16 %z) {
|
||||
; CHECK-LABEL: rotl_i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $5, 15
|
||||
; CHECK-NEXT: sllv $1, $4, $1
|
||||
; CHECK-NEXT: negu $2, $5
|
||||
; CHECK-NEXT: andi $2, $2, 15
|
||||
; CHECK-NEXT: andi $3, $4, 65535
|
||||
; CHECK-NEXT: srlv $2, $3, $2
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $1, $2
|
||||
%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
|
||||
ret i16 %f
|
||||
}
|
||||
|
||||
define i32 @rotl_i32(i32 %x, i32 %z) {
|
||||
; CHECK-LABEL: rotl_i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $5, 31
|
||||
; CHECK-NEXT: sllv $1, $4, $1
|
||||
; CHECK-NEXT: negu $2, $5
|
||||
; CHECK-NEXT: andi $2, $2, 31
|
||||
; CHECK-NEXT: srlv $2, $4, $2
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $1, $2
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define i64 @rotl_i64(i64 %x, i64 %z) {
|
||||
; CHECK-BE-LABEL: rotl_i64:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: negu $1, $7
|
||||
; CHECK-BE-NEXT: andi $3, $1, 63
|
||||
; CHECK-BE-NEXT: srlv $6, $4, $3
|
||||
; CHECK-BE-NEXT: andi $1, $1, 32
|
||||
; CHECK-BE-NEXT: andi $2, $7, 63
|
||||
; CHECK-BE-NEXT: move $8, $6
|
||||
; CHECK-BE-NEXT: movn $8, $zero, $1
|
||||
; CHECK-BE-NEXT: sllv $9, $4, $2
|
||||
; CHECK-BE-NEXT: srl $10, $5, 1
|
||||
; CHECK-BE-NEXT: not $11, $2
|
||||
; CHECK-BE-NEXT: srlv $10, $10, $11
|
||||
; CHECK-BE-NEXT: or $9, $9, $10
|
||||
; CHECK-BE-NEXT: sllv $10, $5, $2
|
||||
; CHECK-BE-NEXT: andi $7, $7, 32
|
||||
; CHECK-BE-NEXT: movn $9, $10, $7
|
||||
; CHECK-BE-NEXT: or $2, $9, $8
|
||||
; CHECK-BE-NEXT: srlv $5, $5, $3
|
||||
; CHECK-BE-NEXT: not $3, $3
|
||||
; CHECK-BE-NEXT: sll $4, $4, 1
|
||||
; CHECK-BE-NEXT: sllv $3, $4, $3
|
||||
; CHECK-BE-NEXT: or $3, $3, $5
|
||||
; CHECK-BE-NEXT: movn $3, $6, $1
|
||||
; CHECK-BE-NEXT: movn $10, $zero, $7
|
||||
; CHECK-BE-NEXT: jr $ra
|
||||
; CHECK-BE-NEXT: or $3, $10, $3
|
||||
;
|
||||
; CHECK-LE-LABEL: rotl_i64:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: negu $1, $6
|
||||
; CHECK-LE-NEXT: andi $2, $1, 63
|
||||
; CHECK-LE-NEXT: srlv $7, $5, $2
|
||||
; CHECK-LE-NEXT: andi $1, $1, 32
|
||||
; CHECK-LE-NEXT: andi $3, $6, 63
|
||||
; CHECK-LE-NEXT: move $8, $7
|
||||
; CHECK-LE-NEXT: movn $8, $zero, $1
|
||||
; CHECK-LE-NEXT: sllv $9, $5, $3
|
||||
; CHECK-LE-NEXT: srl $10, $4, 1
|
||||
; CHECK-LE-NEXT: not $11, $3
|
||||
; CHECK-LE-NEXT: srlv $10, $10, $11
|
||||
; CHECK-LE-NEXT: or $9, $9, $10
|
||||
; CHECK-LE-NEXT: sllv $10, $4, $3
|
||||
; CHECK-LE-NEXT: andi $6, $6, 32
|
||||
; CHECK-LE-NEXT: movn $9, $10, $6
|
||||
; CHECK-LE-NEXT: or $3, $9, $8
|
||||
; CHECK-LE-NEXT: srlv $4, $4, $2
|
||||
; CHECK-LE-NEXT: not $2, $2
|
||||
; CHECK-LE-NEXT: sll $5, $5, 1
|
||||
; CHECK-LE-NEXT: sllv $2, $5, $2
|
||||
; CHECK-LE-NEXT: or $2, $2, $4
|
||||
; CHECK-LE-NEXT: movn $2, $7, $1
|
||||
; CHECK-LE-NEXT: movn $10, $zero, $6
|
||||
; CHECK-LE-NEXT: jr $ra
|
||||
; CHECK-LE-NEXT: or $2, $10, $2
|
||||
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; Vector rotate.
|
||||
|
||||
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
|
||||
; CHECK-LABEL: rotl_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lw $1, 24($sp)
|
||||
; CHECK-NEXT: negu $2, $1
|
||||
; CHECK-NEXT: lw $3, 20($sp)
|
||||
; CHECK-NEXT: negu $8, $3
|
||||
; CHECK-NEXT: andi $8, $8, 31
|
||||
; CHECK-NEXT: andi $2, $2, 31
|
||||
; CHECK-NEXT: andi $3, $3, 31
|
||||
; CHECK-NEXT: andi $1, $1, 31
|
||||
; CHECK-NEXT: lw $9, 16($sp)
|
||||
; CHECK-NEXT: sllv $1, $6, $1
|
||||
; CHECK-NEXT: srlv $6, $6, $2
|
||||
; CHECK-NEXT: sllv $3, $5, $3
|
||||
; CHECK-NEXT: srlv $5, $5, $8
|
||||
; CHECK-NEXT: andi $2, $9, 31
|
||||
; CHECK-NEXT: sllv $2, $4, $2
|
||||
; CHECK-NEXT: negu $8, $9
|
||||
; CHECK-NEXT: andi $8, $8, 31
|
||||
; CHECK-NEXT: srlv $4, $4, $8
|
||||
; CHECK-NEXT: lw $8, 28($sp)
|
||||
; CHECK-NEXT: or $2, $2, $4
|
||||
; CHECK-NEXT: or $3, $3, $5
|
||||
; CHECK-NEXT: or $4, $1, $6
|
||||
; CHECK-NEXT: andi $1, $8, 31
|
||||
; CHECK-NEXT: sllv $1, $7, $1
|
||||
; CHECK-NEXT: negu $5, $8
|
||||
; CHECK-NEXT: andi $5, $5, 31
|
||||
; CHECK-NEXT: srlv $5, $7, $5
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $5, $1, $5
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
; Vector rotate by constant splat amount.
|
||||
|
||||
define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {
|
||||
; CHECK-LABEL: rotl_v4i32_rotl_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: srl $1, $5, 29
|
||||
; CHECK-NEXT: sll $3, $5, 3
|
||||
; CHECK-NEXT: srl $2, $4, 29
|
||||
; CHECK-NEXT: sll $4, $4, 3
|
||||
; CHECK-NEXT: or $2, $4, $2
|
||||
; CHECK-NEXT: or $3, $3, $1
|
||||
; CHECK-NEXT: srl $1, $6, 29
|
||||
; CHECK-NEXT: sll $4, $6, 3
|
||||
; CHECK-NEXT: or $4, $4, $1
|
||||
; CHECK-NEXT: srl $1, $7, 29
|
||||
; CHECK-NEXT: sll $5, $7, 3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $5, $5, $1
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
; Repeat everything for funnel shift right.
|
||||
|
||||
; When first 2 operands match, it's a rotate.
|
||||
|
||||
define i8 @rotr_i8_const_shift(i8 %x) {
|
||||
; CHECK-LABEL: rotr_i8_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: sll $1, $4, 5
|
||||
; CHECK-NEXT: andi $2, $4, 248
|
||||
; CHECK-NEXT: srl $2, $2, 3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i32 @rotr_i32_const_shift(i32 %x) {
|
||||
; CHECK-LABEL: rotr_i32_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: sll $1, $4, 29
|
||||
; CHECK-NEXT: srl $2, $4, 3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; When first 2 operands match, it's a rotate (by variable amount).
|
||||
|
||||
define i16 @rotr_i16(i16 %x, i16 %z) {
|
||||
; CHECK-LABEL: rotr_i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $5, 15
|
||||
; CHECK-NEXT: andi $2, $4, 65535
|
||||
; CHECK-NEXT: srlv $1, $2, $1
|
||||
; CHECK-NEXT: negu $2, $5
|
||||
; CHECK-NEXT: andi $2, $2, 15
|
||||
; CHECK-NEXT: sllv $2, $4, $2
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $1, $2
|
||||
%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
|
||||
ret i16 %f
|
||||
}
|
||||
|
||||
define i32 @rotr_i32(i32 %x, i32 %z) {
|
||||
; CHECK-LABEL: rotr_i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $5, 31
|
||||
; CHECK-NEXT: srlv $1, $4, $1
|
||||
; CHECK-NEXT: negu $2, $5
|
||||
; CHECK-NEXT: andi $2, $2, 31
|
||||
; CHECK-NEXT: sllv $2, $4, $2
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $1, $2
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define i64 @rotr_i64(i64 %x, i64 %z) {
|
||||
; CHECK-BE-LABEL: rotr_i64:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: negu $1, $7
|
||||
; CHECK-BE-NEXT: andi $2, $1, 63
|
||||
; CHECK-BE-NEXT: sllv $6, $5, $2
|
||||
; CHECK-BE-NEXT: andi $1, $1, 32
|
||||
; CHECK-BE-NEXT: andi $3, $7, 63
|
||||
; CHECK-BE-NEXT: move $8, $6
|
||||
; CHECK-BE-NEXT: movn $8, $zero, $1
|
||||
; CHECK-BE-NEXT: srlv $9, $5, $3
|
||||
; CHECK-BE-NEXT: sll $10, $4, 1
|
||||
; CHECK-BE-NEXT: not $11, $3
|
||||
; CHECK-BE-NEXT: sllv $10, $10, $11
|
||||
; CHECK-BE-NEXT: or $9, $10, $9
|
||||
; CHECK-BE-NEXT: srlv $10, $4, $3
|
||||
; CHECK-BE-NEXT: andi $7, $7, 32
|
||||
; CHECK-BE-NEXT: movn $9, $10, $7
|
||||
; CHECK-BE-NEXT: or $3, $9, $8
|
||||
; CHECK-BE-NEXT: sllv $4, $4, $2
|
||||
; CHECK-BE-NEXT: not $2, $2
|
||||
; CHECK-BE-NEXT: srl $5, $5, 1
|
||||
; CHECK-BE-NEXT: srlv $2, $5, $2
|
||||
; CHECK-BE-NEXT: or $2, $4, $2
|
||||
; CHECK-BE-NEXT: movn $2, $6, $1
|
||||
; CHECK-BE-NEXT: movn $10, $zero, $7
|
||||
; CHECK-BE-NEXT: jr $ra
|
||||
; CHECK-BE-NEXT: or $2, $10, $2
|
||||
;
|
||||
; CHECK-LE-LABEL: rotr_i64:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: negu $1, $6
|
||||
; CHECK-LE-NEXT: andi $3, $1, 63
|
||||
; CHECK-LE-NEXT: sllv $7, $4, $3
|
||||
; CHECK-LE-NEXT: andi $1, $1, 32
|
||||
; CHECK-LE-NEXT: andi $2, $6, 63
|
||||
; CHECK-LE-NEXT: move $8, $7
|
||||
; CHECK-LE-NEXT: movn $8, $zero, $1
|
||||
; CHECK-LE-NEXT: srlv $9, $4, $2
|
||||
; CHECK-LE-NEXT: sll $10, $5, 1
|
||||
; CHECK-LE-NEXT: not $11, $2
|
||||
; CHECK-LE-NEXT: sllv $10, $10, $11
|
||||
; CHECK-LE-NEXT: or $9, $10, $9
|
||||
; CHECK-LE-NEXT: srlv $10, $5, $2
|
||||
; CHECK-LE-NEXT: andi $6, $6, 32
|
||||
; CHECK-LE-NEXT: movn $9, $10, $6
|
||||
; CHECK-LE-NEXT: or $2, $9, $8
|
||||
; CHECK-LE-NEXT: sllv $5, $5, $3
|
||||
; CHECK-LE-NEXT: not $3, $3
|
||||
; CHECK-LE-NEXT: srl $4, $4, 1
|
||||
; CHECK-LE-NEXT: srlv $3, $4, $3
|
||||
; CHECK-LE-NEXT: or $3, $5, $3
|
||||
; CHECK-LE-NEXT: movn $3, $7, $1
|
||||
; CHECK-LE-NEXT: movn $10, $zero, $6
|
||||
; CHECK-LE-NEXT: jr $ra
|
||||
; CHECK-LE-NEXT: or $3, $10, $3
|
||||
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; Vector rotate.
|
||||
|
||||
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
|
||||
; CHECK-LABEL: rotr_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lw $1, 24($sp)
|
||||
; CHECK-NEXT: negu $2, $1
|
||||
; CHECK-NEXT: lw $3, 20($sp)
|
||||
; CHECK-NEXT: negu $8, $3
|
||||
; CHECK-NEXT: andi $8, $8, 31
|
||||
; CHECK-NEXT: andi $2, $2, 31
|
||||
; CHECK-NEXT: andi $3, $3, 31
|
||||
; CHECK-NEXT: andi $1, $1, 31
|
||||
; CHECK-NEXT: lw $9, 16($sp)
|
||||
; CHECK-NEXT: srlv $1, $6, $1
|
||||
; CHECK-NEXT: sllv $6, $6, $2
|
||||
; CHECK-NEXT: srlv $3, $5, $3
|
||||
; CHECK-NEXT: sllv $5, $5, $8
|
||||
; CHECK-NEXT: andi $2, $9, 31
|
||||
; CHECK-NEXT: srlv $2, $4, $2
|
||||
; CHECK-NEXT: negu $8, $9
|
||||
; CHECK-NEXT: andi $8, $8, 31
|
||||
; CHECK-NEXT: sllv $4, $4, $8
|
||||
; CHECK-NEXT: lw $8, 28($sp)
|
||||
; CHECK-NEXT: or $2, $2, $4
|
||||
; CHECK-NEXT: or $3, $3, $5
|
||||
; CHECK-NEXT: or $4, $1, $6
|
||||
; CHECK-NEXT: andi $1, $8, 31
|
||||
; CHECK-NEXT: srlv $1, $7, $1
|
||||
; CHECK-NEXT: negu $5, $8
|
||||
; CHECK-NEXT: andi $5, $5, 31
|
||||
; CHECK-NEXT: sllv $5, $7, $5
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $5, $1, $5
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
; Vector rotate by constant splat amount.
|
||||
|
||||
define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
|
||||
; CHECK-LABEL: rotr_v4i32_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: sll $1, $5, 29
|
||||
; CHECK-NEXT: srl $3, $5, 3
|
||||
; CHECK-NEXT: sll $2, $4, 29
|
||||
; CHECK-NEXT: srl $4, $4, 3
|
||||
; CHECK-NEXT: or $2, $4, $2
|
||||
; CHECK-NEXT: or $3, $3, $1
|
||||
; CHECK-NEXT: sll $1, $6, 29
|
||||
; CHECK-NEXT: srl $4, $6, 3
|
||||
; CHECK-NEXT: or $4, $4, $1
|
||||
; CHECK-NEXT: sll $1, $7, 29
|
||||
; CHECK-NEXT: srl $5, $7, 3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $5, $5, $1
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
|
||||
; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $2, $4
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
|
||||
; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $2, $4
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
|
||||
; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: move $2, $4
|
||||
; CHECK-NEXT: move $3, $5
|
||||
; CHECK-NEXT: move $4, $6
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $5, $7
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
|
||||
; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: move $2, $4
|
||||
; CHECK-NEXT: move $3, $5
|
||||
; CHECK-NEXT: move $4, $6
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $5, $7
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
601
test/CodeGen/Mips/funnel-shift.ll
Normal file
601
test/CodeGen/Mips/funnel-shift.ll
Normal file
@ -0,0 +1,601 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=mips-linux-gnu -march=mips -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE
|
||||
; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE
|
||||
|
||||
declare i8 @llvm.fshl.i8(i8, i8, i8)
|
||||
declare i16 @llvm.fshl.i16(i16, i16, i16)
|
||||
declare i32 @llvm.fshl.i32(i32, i32, i32)
|
||||
declare i64 @llvm.fshl.i64(i64, i64, i64)
|
||||
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
|
||||
|
||||
declare i8 @llvm.fshr.i8(i8, i8, i8)
|
||||
declare i16 @llvm.fshr.i16(i16, i16, i16)
|
||||
declare i32 @llvm.fshr.i32(i32, i32, i32)
|
||||
declare i64 @llvm.fshr.i64(i64, i64, i64)
|
||||
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
|
||||
|
||||
; General case - all operands can be variables.
|
||||
|
||||
define i16 @fshl_i16(i16 %x, i16 %y, i16 %z) {
|
||||
; CHECK-LABEL: fshl_i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $6, 15
|
||||
; CHECK-NEXT: sllv $2, $4, $1
|
||||
; CHECK-NEXT: sll $3, $5, 16
|
||||
; CHECK-NEXT: srl $3, $3, 1
|
||||
; CHECK-NEXT: not $1, $1
|
||||
; CHECK-NEXT: andi $1, $1, 31
|
||||
; CHECK-NEXT: srlv $1, $3, $1
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i16 @llvm.fshl.i16(i16 %x, i16 %y, i16 %z)
|
||||
ret i16 %f
|
||||
}
|
||||
|
||||
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
|
||||
; CHECK-LABEL: fshl_i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $6, 31
|
||||
; CHECK-NEXT: sllv $1, $4, $1
|
||||
; CHECK-NEXT: srl $2, $5, 1
|
||||
; CHECK-NEXT: not $3, $6
|
||||
; CHECK-NEXT: andi $3, $3, 31
|
||||
; CHECK-NEXT: srlv $2, $2, $3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $1, $2
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Verify that weird types are minimally supported.
|
||||
declare i37 @llvm.fshl.i37(i37, i37, i37)
|
||||
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
|
||||
; CHECK-BE-LABEL: fshl_i37:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: addiu $sp, $sp, -40
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_offset 40
|
||||
; CHECK-BE-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $19, 32($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $18, 28($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $17, 24($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $16, 20($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: .cfi_offset 31, -4
|
||||
; CHECK-BE-NEXT: .cfi_offset 19, -8
|
||||
; CHECK-BE-NEXT: .cfi_offset 18, -12
|
||||
; CHECK-BE-NEXT: .cfi_offset 17, -16
|
||||
; CHECK-BE-NEXT: .cfi_offset 16, -20
|
||||
; CHECK-BE-NEXT: move $16, $7
|
||||
; CHECK-BE-NEXT: move $17, $6
|
||||
; CHECK-BE-NEXT: move $18, $5
|
||||
; CHECK-BE-NEXT: move $19, $4
|
||||
; CHECK-BE-NEXT: lw $4, 56($sp)
|
||||
; CHECK-BE-NEXT: lw $5, 60($sp)
|
||||
; CHECK-BE-NEXT: addiu $6, $zero, 0
|
||||
; CHECK-BE-NEXT: jal __umoddi3
|
||||
; CHECK-BE-NEXT: addiu $7, $zero, 37
|
||||
; CHECK-BE-NEXT: not $1, $3
|
||||
; CHECK-BE-NEXT: andi $2, $3, 63
|
||||
; CHECK-BE-NEXT: not $4, $2
|
||||
; CHECK-BE-NEXT: srl $5, $18, 1
|
||||
; CHECK-BE-NEXT: sllv $6, $19, $2
|
||||
; CHECK-BE-NEXT: srlv $4, $5, $4
|
||||
; CHECK-BE-NEXT: andi $5, $1, 63
|
||||
; CHECK-BE-NEXT: srl $7, $16, 5
|
||||
; CHECK-BE-NEXT: sll $8, $17, 27
|
||||
; CHECK-BE-NEXT: or $7, $8, $7
|
||||
; CHECK-BE-NEXT: srl $8, $7, 1
|
||||
; CHECK-BE-NEXT: srlv $9, $8, $5
|
||||
; CHECK-BE-NEXT: andi $1, $1, 32
|
||||
; CHECK-BE-NEXT: move $10, $9
|
||||
; CHECK-BE-NEXT: movn $10, $zero, $1
|
||||
; CHECK-BE-NEXT: or $4, $6, $4
|
||||
; CHECK-BE-NEXT: sllv $6, $18, $2
|
||||
; CHECK-BE-NEXT: andi $3, $3, 32
|
||||
; CHECK-BE-NEXT: movn $4, $6, $3
|
||||
; CHECK-BE-NEXT: sll $7, $7, 31
|
||||
; CHECK-BE-NEXT: sll $2, $16, 27
|
||||
; CHECK-BE-NEXT: srl $11, $2, 1
|
||||
; CHECK-BE-NEXT: or $2, $4, $10
|
||||
; CHECK-BE-NEXT: movn $6, $zero, $3
|
||||
; CHECK-BE-NEXT: or $3, $11, $7
|
||||
; CHECK-BE-NEXT: srlv $3, $3, $5
|
||||
; CHECK-BE-NEXT: not $4, $5
|
||||
; CHECK-BE-NEXT: sll $5, $8, 1
|
||||
; CHECK-BE-NEXT: sllv $4, $5, $4
|
||||
; CHECK-BE-NEXT: or $3, $4, $3
|
||||
; CHECK-BE-NEXT: movn $3, $9, $1
|
||||
; CHECK-BE-NEXT: or $3, $6, $3
|
||||
; CHECK-BE-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $17, 24($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $18, 28($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $19, 32($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: jr $ra
|
||||
; CHECK-BE-NEXT: addiu $sp, $sp, 40
|
||||
;
|
||||
; CHECK-LE-LABEL: fshl_i37:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: addiu $sp, $sp, -40
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_offset 40
|
||||
; CHECK-LE-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $19, 32($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $18, 28($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $17, 24($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $16, 20($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: .cfi_offset 31, -4
|
||||
; CHECK-LE-NEXT: .cfi_offset 19, -8
|
||||
; CHECK-LE-NEXT: .cfi_offset 18, -12
|
||||
; CHECK-LE-NEXT: .cfi_offset 17, -16
|
||||
; CHECK-LE-NEXT: .cfi_offset 16, -20
|
||||
; CHECK-LE-NEXT: move $16, $7
|
||||
; CHECK-LE-NEXT: move $17, $6
|
||||
; CHECK-LE-NEXT: move $18, $5
|
||||
; CHECK-LE-NEXT: move $19, $4
|
||||
; CHECK-LE-NEXT: lw $4, 56($sp)
|
||||
; CHECK-LE-NEXT: lw $5, 60($sp)
|
||||
; CHECK-LE-NEXT: addiu $6, $zero, 37
|
||||
; CHECK-LE-NEXT: jal __umoddi3
|
||||
; CHECK-LE-NEXT: addiu $7, $zero, 0
|
||||
; CHECK-LE-NEXT: not $1, $2
|
||||
; CHECK-LE-NEXT: andi $3, $2, 63
|
||||
; CHECK-LE-NEXT: not $4, $3
|
||||
; CHECK-LE-NEXT: srl $5, $19, 1
|
||||
; CHECK-LE-NEXT: sllv $6, $18, $3
|
||||
; CHECK-LE-NEXT: srlv $4, $5, $4
|
||||
; CHECK-LE-NEXT: andi $5, $1, 63
|
||||
; CHECK-LE-NEXT: srl $7, $17, 5
|
||||
; CHECK-LE-NEXT: sll $8, $16, 27
|
||||
; CHECK-LE-NEXT: or $7, $8, $7
|
||||
; CHECK-LE-NEXT: srl $8, $7, 1
|
||||
; CHECK-LE-NEXT: srlv $9, $8, $5
|
||||
; CHECK-LE-NEXT: andi $1, $1, 32
|
||||
; CHECK-LE-NEXT: move $10, $9
|
||||
; CHECK-LE-NEXT: movn $10, $zero, $1
|
||||
; CHECK-LE-NEXT: or $4, $6, $4
|
||||
; CHECK-LE-NEXT: sllv $6, $19, $3
|
||||
; CHECK-LE-NEXT: andi $2, $2, 32
|
||||
; CHECK-LE-NEXT: movn $4, $6, $2
|
||||
; CHECK-LE-NEXT: sll $7, $7, 31
|
||||
; CHECK-LE-NEXT: sll $3, $17, 27
|
||||
; CHECK-LE-NEXT: srl $11, $3, 1
|
||||
; CHECK-LE-NEXT: or $3, $4, $10
|
||||
; CHECK-LE-NEXT: movn $6, $zero, $2
|
||||
; CHECK-LE-NEXT: or $2, $11, $7
|
||||
; CHECK-LE-NEXT: srlv $2, $2, $5
|
||||
; CHECK-LE-NEXT: not $4, $5
|
||||
; CHECK-LE-NEXT: sll $5, $8, 1
|
||||
; CHECK-LE-NEXT: sllv $4, $5, $4
|
||||
; CHECK-LE-NEXT: or $2, $4, $2
|
||||
; CHECK-LE-NEXT: movn $2, $9, $1
|
||||
; CHECK-LE-NEXT: or $2, $6, $2
|
||||
; CHECK-LE-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $17, 24($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $18, 28($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $19, 32($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: jr $ra
|
||||
; CHECK-LE-NEXT: addiu $sp, $sp, 40
|
||||
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
|
||||
ret i37 %f
|
||||
}
|
||||
|
||||
; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
|
||||
|
||||
declare i7 @llvm.fshl.i7(i7, i7, i7)
|
||||
define i7 @fshl_i7_const_fold() {
|
||||
; CHECK-LABEL: fshl_i7_const_fold:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 67
|
||||
%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
|
||||
ret i7 %f
|
||||
}
|
||||
|
||||
define i8 @fshl_i8_const_fold_overshift_1() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 128
|
||||
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshl_i8_const_fold_overshift_2() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold_overshift_2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 120
|
||||
%f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshl_i8_const_fold_overshift_3() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold_overshift_3:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 0
|
||||
%f = call i8 @llvm.fshl.i8(i8 0, i8 225, i8 8)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
; With constant shift amount, this is 'extr'.
|
||||
|
||||
define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshl_i32_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: srl $1, $5, 23
|
||||
; CHECK-NEXT: sll $2, $4, 9
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Check modulo math on shift amount.
|
||||
|
||||
define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshl_i32_const_overshift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: srl $1, $5, 23
|
||||
; CHECK-NEXT: sll $2, $4, 9
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; 64-bit should also work.
|
||||
|
||||
define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
|
||||
; CHECK-BE-LABEL: fshl_i64_const_overshift:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: srl $1, $6, 23
|
||||
; CHECK-BE-NEXT: sll $2, $5, 9
|
||||
; CHECK-BE-NEXT: or $2, $2, $1
|
||||
; CHECK-BE-NEXT: sll $1, $6, 9
|
||||
; CHECK-BE-NEXT: srl $3, $7, 23
|
||||
; CHECK-BE-NEXT: jr $ra
|
||||
; CHECK-BE-NEXT: or $3, $3, $1
|
||||
;
|
||||
; CHECK-LE-LABEL: fshl_i64_const_overshift:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: sll $1, $7, 9
|
||||
; CHECK-LE-NEXT: srl $2, $6, 23
|
||||
; CHECK-LE-NEXT: or $2, $2, $1
|
||||
; CHECK-LE-NEXT: srl $1, $7, 23
|
||||
; CHECK-LE-NEXT: sll $3, $4, 9
|
||||
; CHECK-LE-NEXT: jr $ra
|
||||
; CHECK-LE-NEXT: or $3, $3, $1
|
||||
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; This should work without any node-specific logic.
|
||||
|
||||
define i8 @fshl_i8_const_fold() {
|
||||
; CHECK-LABEL: fshl_i8_const_fold:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 128
|
||||
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
; Repeat everything for funnel shift right.
|
||||
|
||||
; General case - all operands can be variables.
|
||||
|
||||
define i16 @fshr_i16(i16 %x, i16 %y, i16 %z) {
|
||||
; CHECK-LABEL: fshr_i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: sll $1, $5, 16
|
||||
; CHECK-NEXT: andi $2, $6, 15
|
||||
; CHECK-NEXT: ori $3, $2, 16
|
||||
; CHECK-NEXT: srlv $1, $1, $3
|
||||
; CHECK-NEXT: sll $3, $4, 1
|
||||
; CHECK-NEXT: xori $2, $2, 15
|
||||
; CHECK-NEXT: sllv $2, $3, $2
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i16 @llvm.fshr.i16(i16 %x, i16 %y, i16 %z)
|
||||
ret i16 %f
|
||||
}
|
||||
|
||||
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
|
||||
; CHECK-LABEL: fshr_i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: andi $1, $6, 31
|
||||
; CHECK-NEXT: srlv $1, $5, $1
|
||||
; CHECK-NEXT: sll $2, $4, 1
|
||||
; CHECK-NEXT: not $3, $6
|
||||
; CHECK-NEXT: andi $3, $3, 31
|
||||
; CHECK-NEXT: sllv $2, $2, $3
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Verify that weird types are minimally supported.
|
||||
declare i37 @llvm.fshr.i37(i37, i37, i37)
|
||||
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
|
||||
; CHECK-BE-LABEL: fshr_i37:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: addiu $sp, $sp, -40
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_offset 40
|
||||
; CHECK-BE-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $19, 32($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $18, 28($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $17, 24($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: sw $16, 20($sp) # 4-byte Folded Spill
|
||||
; CHECK-BE-NEXT: .cfi_offset 31, -4
|
||||
; CHECK-BE-NEXT: .cfi_offset 19, -8
|
||||
; CHECK-BE-NEXT: .cfi_offset 18, -12
|
||||
; CHECK-BE-NEXT: .cfi_offset 17, -16
|
||||
; CHECK-BE-NEXT: .cfi_offset 16, -20
|
||||
; CHECK-BE-NEXT: move $16, $7
|
||||
; CHECK-BE-NEXT: move $17, $6
|
||||
; CHECK-BE-NEXT: move $18, $5
|
||||
; CHECK-BE-NEXT: move $19, $4
|
||||
; CHECK-BE-NEXT: lw $4, 56($sp)
|
||||
; CHECK-BE-NEXT: lw $5, 60($sp)
|
||||
; CHECK-BE-NEXT: addiu $6, $zero, 0
|
||||
; CHECK-BE-NEXT: jal __umoddi3
|
||||
; CHECK-BE-NEXT: addiu $7, $zero, 37
|
||||
; CHECK-BE-NEXT: addiu $1, $3, 27
|
||||
; CHECK-BE-NEXT: andi $2, $1, 63
|
||||
; CHECK-BE-NEXT: not $3, $2
|
||||
; CHECK-BE-NEXT: srl $4, $16, 5
|
||||
; CHECK-BE-NEXT: sll $5, $17, 27
|
||||
; CHECK-BE-NEXT: or $4, $5, $4
|
||||
; CHECK-BE-NEXT: sll $5, $4, 1
|
||||
; CHECK-BE-NEXT: sll $6, $16, 27
|
||||
; CHECK-BE-NEXT: srlv $6, $6, $2
|
||||
; CHECK-BE-NEXT: sllv $3, $5, $3
|
||||
; CHECK-BE-NEXT: not $5, $1
|
||||
; CHECK-BE-NEXT: andi $7, $5, 63
|
||||
; CHECK-BE-NEXT: sll $8, $18, 1
|
||||
; CHECK-BE-NEXT: sllv $8, $8, $7
|
||||
; CHECK-BE-NEXT: andi $5, $5, 32
|
||||
; CHECK-BE-NEXT: move $9, $8
|
||||
; CHECK-BE-NEXT: movn $9, $zero, $5
|
||||
; CHECK-BE-NEXT: or $3, $3, $6
|
||||
; CHECK-BE-NEXT: srlv $2, $4, $2
|
||||
; CHECK-BE-NEXT: andi $1, $1, 32
|
||||
; CHECK-BE-NEXT: movn $3, $2, $1
|
||||
; CHECK-BE-NEXT: srl $4, $18, 31
|
||||
; CHECK-BE-NEXT: sll $6, $19, 1
|
||||
; CHECK-BE-NEXT: or $4, $6, $4
|
||||
; CHECK-BE-NEXT: or $3, $9, $3
|
||||
; CHECK-BE-NEXT: movn $2, $zero, $1
|
||||
; CHECK-BE-NEXT: sllv $1, $4, $7
|
||||
; CHECK-BE-NEXT: not $4, $7
|
||||
; CHECK-BE-NEXT: lui $6, 32767
|
||||
; CHECK-BE-NEXT: ori $6, $6, 65535
|
||||
; CHECK-BE-NEXT: and $6, $18, $6
|
||||
; CHECK-BE-NEXT: srlv $4, $6, $4
|
||||
; CHECK-BE-NEXT: or $1, $1, $4
|
||||
; CHECK-BE-NEXT: movn $1, $8, $5
|
||||
; CHECK-BE-NEXT: or $2, $1, $2
|
||||
; CHECK-BE-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $17, 24($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $18, 28($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $19, 32($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
||||
; CHECK-BE-NEXT: jr $ra
|
||||
; CHECK-BE-NEXT: addiu $sp, $sp, 40
|
||||
;
|
||||
; CHECK-LE-LABEL: fshr_i37:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: addiu $sp, $sp, -40
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_offset 40
|
||||
; CHECK-LE-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $19, 32($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $18, 28($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $17, 24($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: sw $16, 20($sp) # 4-byte Folded Spill
|
||||
; CHECK-LE-NEXT: .cfi_offset 31, -4
|
||||
; CHECK-LE-NEXT: .cfi_offset 19, -8
|
||||
; CHECK-LE-NEXT: .cfi_offset 18, -12
|
||||
; CHECK-LE-NEXT: .cfi_offset 17, -16
|
||||
; CHECK-LE-NEXT: .cfi_offset 16, -20
|
||||
; CHECK-LE-NEXT: move $16, $7
|
||||
; CHECK-LE-NEXT: move $17, $6
|
||||
; CHECK-LE-NEXT: move $18, $5
|
||||
; CHECK-LE-NEXT: move $19, $4
|
||||
; CHECK-LE-NEXT: lw $4, 56($sp)
|
||||
; CHECK-LE-NEXT: lw $5, 60($sp)
|
||||
; CHECK-LE-NEXT: addiu $6, $zero, 37
|
||||
; CHECK-LE-NEXT: jal __umoddi3
|
||||
; CHECK-LE-NEXT: addiu $7, $zero, 0
|
||||
; CHECK-LE-NEXT: addiu $1, $2, 27
|
||||
; CHECK-LE-NEXT: andi $2, $1, 63
|
||||
; CHECK-LE-NEXT: not $3, $2
|
||||
; CHECK-LE-NEXT: srl $4, $17, 5
|
||||
; CHECK-LE-NEXT: sll $5, $16, 27
|
||||
; CHECK-LE-NEXT: or $4, $5, $4
|
||||
; CHECK-LE-NEXT: sll $5, $4, 1
|
||||
; CHECK-LE-NEXT: sll $6, $17, 27
|
||||
; CHECK-LE-NEXT: srlv $6, $6, $2
|
||||
; CHECK-LE-NEXT: sllv $3, $5, $3
|
||||
; CHECK-LE-NEXT: not $5, $1
|
||||
; CHECK-LE-NEXT: andi $7, $5, 63
|
||||
; CHECK-LE-NEXT: sll $8, $19, 1
|
||||
; CHECK-LE-NEXT: sllv $8, $8, $7
|
||||
; CHECK-LE-NEXT: andi $5, $5, 32
|
||||
; CHECK-LE-NEXT: move $9, $8
|
||||
; CHECK-LE-NEXT: movn $9, $zero, $5
|
||||
; CHECK-LE-NEXT: or $3, $3, $6
|
||||
; CHECK-LE-NEXT: srlv $4, $4, $2
|
||||
; CHECK-LE-NEXT: andi $1, $1, 32
|
||||
; CHECK-LE-NEXT: movn $3, $4, $1
|
||||
; CHECK-LE-NEXT: srl $2, $19, 31
|
||||
; CHECK-LE-NEXT: sll $6, $18, 1
|
||||
; CHECK-LE-NEXT: or $6, $6, $2
|
||||
; CHECK-LE-NEXT: or $2, $9, $3
|
||||
; CHECK-LE-NEXT: movn $4, $zero, $1
|
||||
; CHECK-LE-NEXT: sllv $1, $6, $7
|
||||
; CHECK-LE-NEXT: not $3, $7
|
||||
; CHECK-LE-NEXT: lui $6, 32767
|
||||
; CHECK-LE-NEXT: ori $6, $6, 65535
|
||||
; CHECK-LE-NEXT: and $6, $19, $6
|
||||
; CHECK-LE-NEXT: srlv $3, $6, $3
|
||||
; CHECK-LE-NEXT: or $1, $1, $3
|
||||
; CHECK-LE-NEXT: movn $1, $8, $5
|
||||
; CHECK-LE-NEXT: or $3, $1, $4
|
||||
; CHECK-LE-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $17, 24($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $18, 28($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $19, 32($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
||||
; CHECK-LE-NEXT: jr $ra
|
||||
; CHECK-LE-NEXT: addiu $sp, $sp, 40
|
||||
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
|
||||
ret i37 %f
|
||||
}
|
||||
|
||||
; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
|
||||
|
||||
declare i7 @llvm.fshr.i7(i7, i7, i7)
|
||||
define i7 @fshr_i7_const_fold() {
|
||||
; CHECK-LABEL: fshr_i7_const_fold:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 31
|
||||
%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
|
||||
ret i7 %f
|
||||
}
|
||||
|
||||
define i8 @fshr_i8_const_fold_overshift_1() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 254
|
||||
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshr_i8_const_fold_overshift_2() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 225
|
||||
%f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i8 @fshr_i8_const_fold_overshift_3() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 255
|
||||
%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
; With constant shift amount, this is 'extr'.
|
||||
|
||||
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshr_i32_const_shift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: srl $1, $5, 9
|
||||
; CHECK-NEXT: sll $2, $4, 23
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; Check modulo math on shift amount. 41-32=9.
|
||||
|
||||
define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshr_i32_const_overshift:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: srl $1, $5, 9
|
||||
; CHECK-NEXT: sll $2, $4, 23
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: or $2, $2, $1
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
; 64-bit should also work. 105-64 = 41.
|
||||
|
||||
define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
|
||||
; CHECK-BE-LABEL: fshr_i64_const_overshift:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: srl $1, $5, 9
|
||||
; CHECK-BE-NEXT: sll $2, $4, 23
|
||||
; CHECK-BE-NEXT: or $2, $2, $1
|
||||
; CHECK-BE-NEXT: srl $1, $6, 9
|
||||
; CHECK-BE-NEXT: sll $3, $5, 23
|
||||
; CHECK-BE-NEXT: jr $ra
|
||||
; CHECK-BE-NEXT: or $3, $3, $1
|
||||
;
|
||||
; CHECK-LE-LABEL: fshr_i64_const_overshift:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: srl $1, $7, 9
|
||||
; CHECK-LE-NEXT: sll $2, $4, 23
|
||||
; CHECK-LE-NEXT: or $2, $2, $1
|
||||
; CHECK-LE-NEXT: srl $1, $4, 9
|
||||
; CHECK-LE-NEXT: sll $3, $5, 23
|
||||
; CHECK-LE-NEXT: jr $ra
|
||||
; CHECK-LE-NEXT: or $3, $3, $1
|
||||
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
|
||||
ret i64 %f
|
||||
}
|
||||
|
||||
; This should work without any node-specific logic.
|
||||
|
||||
define i8 @fshr_i8_const_fold() {
|
||||
; CHECK-LABEL: fshr_i8_const_fold:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: addiu $2, $zero, 254
|
||||
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
|
||||
ret i8 %f
|
||||
}
|
||||
|
||||
define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $2, $4
|
||||
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: fshr_i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $2, $5
|
||||
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)
|
||||
ret i32 %f
|
||||
}
|
||||
|
||||
define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: move $2, $4
|
||||
; CHECK-NEXT: move $3, $5
|
||||
; CHECK-NEXT: move $4, $6
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: move $5, $7
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-LABEL: fshr_v4i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lw $5, 28($sp)
|
||||
; CHECK-NEXT: lw $4, 24($sp)
|
||||
; CHECK-NEXT: lw $3, 20($sp)
|
||||
; CHECK-NEXT: lw $2, 16($sp)
|
||||
; CHECK-NEXT: jr $ra
|
||||
; CHECK-NEXT: nop
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user