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[DAGCombiner] extractShiftForRotate - fix out of range shift issue
Don't just check for negative shift amounts. Fixes OSS Fuzz #9935 https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=9935 llvm-svn: 340015
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@ -5276,9 +5276,9 @@ static SDValue extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift,
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// Compute the shift amount we need to extract to complete the rotate.
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const unsigned VTWidth = ShiftedVT.getScalarSizeInBits();
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APInt NeededShiftAmt = VTWidth - OppShiftCst->getAPIntValue();
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if (NeededShiftAmt.isNegative())
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if (OppShiftCst->getAPIntValue().ugt(VTWidth))
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return SDValue();
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APInt NeededShiftAmt = VTWidth - OppShiftCst->getAPIntValue();
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// Normalize the bitwidth of the two mul/udiv/shift constant operands.
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APInt ExtractFromAmt = ExtractFromCst->getAPIntValue();
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APInt OppLHSAmt = OppLHSCst->getAPIntValue();
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@ -341,3 +341,16 @@ define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
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%9 = or <4 x i32> %5, %8
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ret <4 x i32> %9
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}
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; OSS Fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=9935
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define i32 @fuzz9935() {
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; CHECK-LABEL: fuzz9935:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%1 = trunc i40 549755813887 to i32
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%2 = mul i32 %1, %1
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%3 = lshr i32 %2, %1
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%4 = or i32 %3, %2
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ret i32 %4
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}
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