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[ARM] Add neon FP16 scalar_to_vector patterns.

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This adds some simple fp16 scalar_to_vector patterns, preventing a
selection failure if this came up.

Differential Revision: https://reviews.llvm.org/D95427
This commit is contained in:
David Green 2021-01-27 09:59:15 +00:00
parent 211141f4c9
commit cfa651ce67
2 changed files with 38 additions and 2 deletions
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7
lib/Target/ARM/ARMInstrNEON.td
View File

@ -6482,8 +6482,6 @@ def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
defm : InsertEltF16<f16, v4f16, v8f16>;
//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
(INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
@ -6494,6 +6492,11 @@ def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
def : Pat<(v4f16 (scalar_to_vector (f16 HPR:$src))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), HPR:$src, ssub_0)>;
def : Pat<(v8f16 (scalar_to_vector (f16 HPR:$src))),
(INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), HPR:$src, ssub_0)>;
def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
(VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
def : Pat<(v4i16 (scalar_to_vector GPR:$src)),

33
test/CodeGen/ARM/fp16-insert-extract.ll
View File

@ -74,6 +74,39 @@ entry:
ret float %conv
}
define <4 x half> @insert_v4f16(half %a) {
; CHECKHARD-LABEL: insert_v4f16:
; CHECKHARD: @ %bb.0: @ %entry
; CHECKHARD-NEXT: @ kill: def $s0 killed $s0 def $d0
; CHECKHARD-NEXT: bx lr
;
; CHECKSOFT-LABEL: insert_v4f16:
; CHECKSOFT: @ %bb.0: @ %entry
; CHECKSOFT-NEXT: vmov.f16 s0, r0
; CHECKSOFT-NEXT: vmov r0, r1, d0
; CHECKSOFT-NEXT: bx lr
entry:
%res = insertelement <4 x half> undef, half %a, i32 0
ret <4 x half> %res
}
define <8 x half> @insert_v8f16(half %a) {
; CHECKHARD-LABEL: insert_v8f16:
; CHECKHARD: @ %bb.0: @ %entry
; CHECKHARD-NEXT: @ kill: def $s0 killed $s0 def $q0
; CHECKHARD-NEXT: bx lr
;
; CHECKSOFT-LABEL: insert_v8f16:
; CHECKSOFT: @ %bb.0: @ %entry
; CHECKSOFT-NEXT: vmov.f16 s0, r0
; CHECKSOFT-NEXT: vmov r2, r3, d1
; CHECKSOFT-NEXT: vmov r0, r1, d0
; CHECKSOFT-NEXT: bx lr
entry:
%res = insertelement <8 x half> undef, half %a, i32 0
ret <8 x half> %res
}
define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
; CHECKHARD-LABEL: test_vset_lane_f16:
; CHECKHARD: @ %bb.0: @ %entry