mirror of
https://github.com/RPCS3/llvm-mirror.git
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[WebAssembly] Add binary-encoding opcode values to instruction descriptions.
llvm-svn: 283389
This commit is contained in:
Dan Gohman
parent
7388fcda39
commit
cfaebd7741
@ -44,6 +44,10 @@ namespace WebAssembly {
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enum OperandType {
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/// Basic block label in a branch construct.
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OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
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/// 32-bit integer immediates.
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OPERAND_I32IMM,
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/// 64-bit integer immediates.
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OPERAND_I64IMM,
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/// 32-bit floating-point immediates.
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OPERAND_F32IMM,
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/// 64-bit floating-point immediates.
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@ -18,14 +18,13 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
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// The condition operand is a boolean value which WebAssembly represents as i32.
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def BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
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[(brcond I32:$cond, bb:$dst)],
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"br_if \t$dst, $cond">;
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"br_if \t$dst, $cond", 0x07>;
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let isCodeGenOnly = 1 in
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def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), [],
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"br_unless\t$dst, $cond">;
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def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), []>;
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let isBarrier = 1 in {
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def BR : I<(outs), (ins bb_op:$dst),
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[(br bb:$dst)],
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"br \t$dst">;
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"br \t$dst", 0x06>;
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} // isBarrier = 1
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} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
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@ -46,7 +45,7 @@ let Defs = [ARGUMENTS] in {
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let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
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def BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
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[(WebAssemblybr_table I32:$index)],
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"br_table \t$index"> {
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"br_table \t$index", 0x08> {
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let TSFlags{0} = 1;
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let TSFlags{1} = 1;
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}
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@ -62,8 +61,8 @@ def BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
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// use/clobber VALUE_STACK to prevent them from being moved into the middle of
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// an expression tree.
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let Uses = [VALUE_STACK], Defs = [VALUE_STACK] in {
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def BLOCK : I<(outs), (ins), [], "block">;
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def LOOP : I<(outs), (ins), [], "loop">;
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def BLOCK : I<(outs), (ins), [], "block", 0x01>;
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def LOOP : I<(outs), (ins), [], "loop", 0x02>;
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def END_BLOCK : I<(outs), (ins), [], "end_block">;
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def END_LOOP : I<(outs), (ins), [], "end_loop">;
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} // Uses = [VALUE_STACK], Defs = [VALUE_STACK]
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@ -17,14 +17,14 @@ let Defs = [ARGUMENTS] in {
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def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src),
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[(set I32:$dst, (trunc I64:$src))],
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"i32.wrap/i64\t$dst, $src">;
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"i32.wrap/i64\t$dst, $src", 0xa1>;
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def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src),
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[(set I64:$dst, (sext I32:$src))],
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"i64.extend_s/i32\t$dst, $src">;
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"i64.extend_s/i32\t$dst, $src", 0xa6>;
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def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src),
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[(set I64:$dst, (zext I32:$src))],
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"i64.extend_u/i32\t$dst, $src">;
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"i64.extend_u/i32\t$dst, $src", 0xa7>;
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} // defs = [ARGUMENTS]
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@ -39,73 +39,73 @@ let Defs = [ARGUMENTS] in {
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let hasSideEffects = 1 in {
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def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_sint F32:$src))],
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"i32.trunc_s/f32\t$dst, $src">;
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"i32.trunc_s/f32\t$dst, $src", 0x9d>;
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def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_uint F32:$src))],
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"i32.trunc_u/f32\t$dst, $src">;
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"i32.trunc_u/f32\t$dst, $src", 0x9f>;
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def I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_sint F32:$src))],
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"i64.trunc_s/f32\t$dst, $src">;
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"i64.trunc_s/f32\t$dst, $src", 0xa2>;
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def I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_uint F32:$src))],
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"i64.trunc_u/f32\t$dst, $src">;
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"i64.trunc_u/f32\t$dst, $src", 0xa4>;
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def I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_sint F64:$src))],
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"i32.trunc_s/f64\t$dst, $src">;
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"i32.trunc_s/f64\t$dst, $src", 0x9e>;
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def I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_uint F64:$src))],
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"i32.trunc_u/f64\t$dst, $src">;
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"i32.trunc_u/f64\t$dst, $src", 0xa0>;
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def I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_sint F64:$src))],
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"i64.trunc_s/f64\t$dst, $src">;
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"i64.trunc_s/f64\t$dst, $src", 0xa3>;
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def I64_TRUNC_U_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_uint F64:$src))],
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"i64.trunc_u/f64\t$dst, $src">;
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"i64.trunc_u/f64\t$dst, $src", 0xa5>;
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} // hasSideEffects = 1
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def F32_CONVERT_S_I32 : I<(outs F32:$dst), (ins I32:$src),
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[(set F32:$dst, (sint_to_fp I32:$src))],
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"f32.convert_s/i32\t$dst, $src">;
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"f32.convert_s/i32\t$dst, $src", 0xa8>;
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def F32_CONVERT_U_I32 : I<(outs F32:$dst), (ins I32:$src),
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[(set F32:$dst, (uint_to_fp I32:$src))],
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"f32.convert_u/i32\t$dst, $src">;
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"f32.convert_u/i32\t$dst, $src", 0xa9>;
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def F64_CONVERT_S_I32 : I<(outs F64:$dst), (ins I32:$src),
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[(set F64:$dst, (sint_to_fp I32:$src))],
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"f64.convert_s/i32\t$dst, $src">;
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"f64.convert_s/i32\t$dst, $src", 0xae>;
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def F64_CONVERT_U_I32 : I<(outs F64:$dst), (ins I32:$src),
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[(set F64:$dst, (uint_to_fp I32:$src))],
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"f64.convert_u/i32\t$dst, $src">;
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"f64.convert_u/i32\t$dst, $src", 0xaf>;
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def F32_CONVERT_S_I64 : I<(outs F32:$dst), (ins I64:$src),
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[(set F32:$dst, (sint_to_fp I64:$src))],
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"f32.convert_s/i64\t$dst, $src">;
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"f32.convert_s/i64\t$dst, $src", 0xaa>;
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def F32_CONVERT_U_I64 : I<(outs F32:$dst), (ins I64:$src),
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[(set F32:$dst, (uint_to_fp I64:$src))],
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"f32.convert_u/i64\t$dst, $src">;
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"f32.convert_u/i64\t$dst, $src", 0xab>;
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def F64_CONVERT_S_I64 : I<(outs F64:$dst), (ins I64:$src),
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[(set F64:$dst, (sint_to_fp I64:$src))],
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"f64.convert_s/i64\t$dst, $src">;
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"f64.convert_s/i64\t$dst, $src", 0xb0>;
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def F64_CONVERT_U_I64 : I<(outs F64:$dst), (ins I64:$src),
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[(set F64:$dst, (uint_to_fp I64:$src))],
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"f64.convert_u/i64\t$dst, $src">;
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"f64.convert_u/i64\t$dst, $src", 0xb1>;
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def F64_PROMOTE_F32 : I<(outs F64:$dst), (ins F32:$src),
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[(set F64:$dst, (fpextend F32:$src))],
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"f64.promote/f32\t$dst, $src">;
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"f64.promote/f32\t$dst, $src", 0xb2>;
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def F32_DEMOTE_F64 : I<(outs F32:$dst), (ins F64:$src),
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[(set F32:$dst, (fpround F64:$src))],
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"f32.demote/f64\t$dst, $src">;
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"f32.demote/f64\t$dst, $src", 0xac>;
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def I32_REINTERPRET_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (bitconvert F32:$src))],
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"i32.reinterpret/f32\t$dst, $src">;
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"i32.reinterpret/f32\t$dst, $src", 0xb4>;
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def F32_REINTERPRET_I32 : I<(outs F32:$dst), (ins I32:$src),
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[(set F32:$dst, (bitconvert I32:$src))],
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"f32.reinterpret/i32\t$dst, $src">;
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"f32.reinterpret/i32\t$dst, $src", 0xad>;
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def I64_REINTERPRET_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (bitconvert F64:$src))],
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"i64.reinterpret/f64\t$dst, $src">;
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"i64.reinterpret/f64\t$dst, $src", 0xb5>;
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def F64_REINTERPRET_I64 : I<(outs F64:$dst), (ins I64:$src),
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[(set F64:$dst, (bitconvert I64:$src))],
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"f64.reinterpret/i64\t$dst, $src">;
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"f64.reinterpret/i64\t$dst, $src", 0xb3>;
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} // Defs = [ARGUMENTS]
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@ -15,26 +15,26 @@
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let Defs = [ARGUMENTS] in {
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let isCommutable = 1 in
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defm ADD : BinaryFP<fadd, "add ">;
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defm SUB : BinaryFP<fsub, "sub ">;
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defm ADD : BinaryFP<fadd, "add ", 0x75, 0x89>;
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defm SUB : BinaryFP<fsub, "sub ", 0x76, 0x8a>;
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let isCommutable = 1 in
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defm MUL : BinaryFP<fmul, "mul ">;
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defm DIV : BinaryFP<fdiv, "div ">;
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defm SQRT : UnaryFP<fsqrt, "sqrt">;
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defm MUL : BinaryFP<fmul, "mul ", 0x77, 0x8b>;
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defm DIV : BinaryFP<fdiv, "div ", 0x78, 0x8c>;
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defm SQRT : UnaryFP<fsqrt, "sqrt", 0x82, 0x96>;
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defm ABS : UnaryFP<fabs, "abs ">;
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defm NEG : UnaryFP<fneg, "neg ">;
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defm COPYSIGN : BinaryFP<fcopysign, "copysign">;
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defm ABS : UnaryFP<fabs, "abs ", 0x7b, 0x8f>;
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defm NEG : UnaryFP<fneg, "neg ", 0x7c, 0x90>;
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defm COPYSIGN : BinaryFP<fcopysign, "copysign", 0x7d, 0x91>;
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let isCommutable = 1 in {
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defm MIN : BinaryFP<fminnan, "min ">;
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defm MAX : BinaryFP<fmaxnan, "max ">;
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defm MIN : BinaryFP<fminnan, "min ", 0x79, 0x8d>;
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defm MAX : BinaryFP<fmaxnan, "max ", 0x7a, 0x8e>;
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} // isCommutable = 1
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defm CEIL : UnaryFP<fceil, "ceil">;
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defm FLOOR : UnaryFP<ffloor, "floor">;
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defm TRUNC : UnaryFP<ftrunc, "trunc">;
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defm NEAREST : UnaryFP<fnearbyint, "nearest">;
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defm CEIL : UnaryFP<fceil, "ceil", 0x7e, 0x92>;
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defm FLOOR : UnaryFP<ffloor, "floor", 0x7f, 0x93>;
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defm TRUNC : UnaryFP<ftrunc, "trunc", 0x80, 0x94>;
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defm NEAREST : UnaryFP<fnearbyint, "nearest", 0x81, 0x95>;
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} // Defs = [ARGUMENTS]
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@ -51,13 +51,13 @@ def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
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let Defs = [ARGUMENTS] in {
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let isCommutable = 1 in {
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defm EQ : ComparisonFP<SETOEQ, "eq ">;
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defm NE : ComparisonFP<SETUNE, "ne ">;
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defm EQ : ComparisonFP<SETOEQ, "eq ", 0x83, 0x97>;
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defm NE : ComparisonFP<SETUNE, "ne ", 0x84, 0x98>;
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} // isCommutable = 1
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defm LT : ComparisonFP<SETOLT, "lt ">;
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defm LE : ComparisonFP<SETOLE, "le ">;
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defm GT : ComparisonFP<SETOGT, "gt ">;
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defm GE : ComparisonFP<SETOGE, "ge ">;
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defm LT : ComparisonFP<SETOLT, "lt ", 0x85, 0x99>;
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defm LE : ComparisonFP<SETOLE, "le ", 0x86, 0x9a>;
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defm GT : ComparisonFP<SETOGT, "gt ", 0x87, 0x9b>;
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defm GE : ComparisonFP<SETOGE, "ge ", 0x88, 0x9c>;
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} // Defs = [ARGUMENTS]
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@ -13,56 +13,57 @@
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format.
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class WebAssemblyInst<string asmstr> : Instruction {
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field bits<0> Inst; // Instruction encoding.
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class WebAssemblyInst<bits<32> inst, string asmstr> : Instruction {
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field bits<32> Inst = inst; // Instruction encoding.
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let Namespace = "WebAssembly";
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let Pattern = [];
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let AsmString = asmstr;
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}
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// Normal instructions.
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class I<dag oops, dag iops, list<dag> pattern, string asmstr = "">
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: WebAssemblyInst<asmstr> {
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class I<dag oops, dag iops, list<dag> pattern, string asmstr = "", bits<32> inst = -1>
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: WebAssemblyInst<inst, asmstr> {
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dag OutOperandList = oops;
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dag InOperandList = iops;
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let Pattern = pattern;
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}
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class SIMD_I<dag oops, dag iops, list<dag> pattern, string asmstr = "">
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: I<oops, iops, pattern, asmstr>, Requires<[HasSIMD128]>;
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class SIMD_I<dag oops, dag iops, list<dag> pattern,
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string asmstr = "", bits<32> inst = -1>
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: I<oops, iops, pattern, asmstr, inst>, Requires<[HasSIMD128]>;
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// Unary and binary instructions, for the local types that WebAssembly supports.
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multiclass UnaryInt<SDNode node, string name> {
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multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst, bits<32> i64Inst> {
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def _I32 : I<(outs I32:$dst), (ins I32:$src),
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[(set I32:$dst, (node I32:$src))],
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!strconcat("i32.", !strconcat(name, "\t$dst, $src"))>;
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!strconcat("i32.", !strconcat(name, "\t$dst, $src")), i32Inst>;
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def _I64 : I<(outs I64:$dst), (ins I64:$src),
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[(set I64:$dst, (node I64:$src))],
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!strconcat("i64.", !strconcat(name, "\t$dst, $src"))>;
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!strconcat("i64.", !strconcat(name, "\t$dst, $src")), i64Inst>;
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}
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multiclass BinaryInt<SDNode node, string name> {
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multiclass BinaryInt<SDNode node, string name, bits<32> i32Inst, bits<32> i64Inst> {
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def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
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[(set I32:$dst, (node I32:$lhs, I32:$rhs))],
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!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")), i32Inst>;
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def _I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs),
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[(set I64:$dst, (node I64:$lhs, I64:$rhs))],
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!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")), i64Inst>;
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}
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multiclass UnaryFP<SDNode node, string name> {
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multiclass UnaryFP<SDNode node, string name, bits<32> f32Inst, bits<32> f64Inst> {
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def _F32 : I<(outs F32:$dst), (ins F32:$src),
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[(set F32:$dst, (node F32:$src))],
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!strconcat("f32.", !strconcat(name, "\t$dst, $src"))>;
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!strconcat("f32.", !strconcat(name, "\t$dst, $src")), f32Inst>;
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def _F64 : I<(outs F64:$dst), (ins F64:$src),
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[(set F64:$dst, (node F64:$src))],
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!strconcat("f64.", !strconcat(name, "\t$dst, $src"))>;
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!strconcat("f64.", !strconcat(name, "\t$dst, $src")), f64Inst>;
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}
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multiclass BinaryFP<SDNode node, string name> {
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multiclass BinaryFP<SDNode node, string name, bits<32> f32Inst, bits<32> f64Inst> {
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def _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs),
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[(set F32:$dst, (node F32:$lhs, F32:$rhs))],
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!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")), f32Inst>;
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def _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs),
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[(set F64:$dst, (node F64:$lhs, F64:$rhs))],
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!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")), f64Inst>;
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}
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multiclass SIMDBinary<SDNode node, SDNode fnode, string name> {
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def _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
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@ -79,19 +80,23 @@ multiclass SIMDBinary<SDNode node, SDNode fnode, string name> {
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!strconcat("f32x4.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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}
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multiclass ComparisonInt<CondCode cond, string name> {
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multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> {
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def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
|
||||
[(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
|
||||
!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
|
||||
!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
|
||||
i32Inst>;
|
||||
def _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs),
|
||||
[(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
|
||||
!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
|
||||
!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
|
||||
i64Inst>;
|
||||
}
|
||||
multiclass ComparisonFP<CondCode cond, string name> {
|
||||
multiclass ComparisonFP<CondCode cond, string name, bits<32> f32Inst, bits<32> f64Inst> {
|
||||
def _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs),
|
||||
[(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
|
||||
!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
|
||||
!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
|
||||
f32Inst>;
|
||||
def _F64 : I<(outs I32:$dst), (ins F64:$lhs, F64:$rhs),
|
||||
[(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
|
||||
!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
|
||||
!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
|
||||
f64Inst>;
|
||||
}
|
||||
|
||||
@ -71,6 +71,12 @@ let OperandNamespace = "WebAssembly" in {
|
||||
let OperandType = "OPERAND_BASIC_BLOCK" in
|
||||
def bb_op : Operand<OtherVT>;
|
||||
|
||||
let OperandType = "OPERAND_I32IMM" in
|
||||
def i32imm_op : Operand<i32>;
|
||||
|
||||
let OperandType = "OPERAND_I64IMM" in
|
||||
def i64imm_op : Operand<i64>;
|
||||
|
||||
let OperandType = "OPERAND_F32IMM" in
|
||||
def f32imm_op : Operand<f32>;
|
||||
|
||||
@ -144,10 +150,10 @@ defm : LOCAL<F64>;
|
||||
defm : LOCAL<V128>, Requires<[HasSIMD128]>;
|
||||
|
||||
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
|
||||
def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm),
|
||||
def CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
|
||||
[(set I32:$res, imm:$imm)],
|
||||
"i32.const\t$res, $imm">;
|
||||
def CONST_I64 : I<(outs I64:$res), (ins i64imm:$imm),
|
||||
def CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
|
||||
[(set I64:$res, imm:$imm)],
|
||||
"i64.const\t$res, $imm">;
|
||||
def CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
|
||||
|
||||
@ -17,51 +17,51 @@ let Defs = [ARGUMENTS] in {
|
||||
// The spaces after the names are for aesthetic purposes only, to make
|
||||
// operands line up vertically after tab expansion.
|
||||
let isCommutable = 1 in
|
||||
defm ADD : BinaryInt<add, "add ">;
|
||||
defm SUB : BinaryInt<sub, "sub ">;
|
||||
defm ADD : BinaryInt<add, "add ", 0x40, 0x5b>;
|
||||
defm SUB : BinaryInt<sub, "sub ", 0x41, 0x5c>;
|
||||
let isCommutable = 1 in
|
||||
defm MUL : BinaryInt<mul, "mul ">;
|
||||
defm MUL : BinaryInt<mul, "mul ", 0x42, 0x5d>;
|
||||
// Divide and remainder trap on a zero denominator.
|
||||
let hasSideEffects = 1 in {
|
||||
defm DIV_S : BinaryInt<sdiv, "div_s">;
|
||||
defm DIV_U : BinaryInt<udiv, "div_u">;
|
||||
defm REM_S : BinaryInt<srem, "rem_s">;
|
||||
defm REM_U : BinaryInt<urem, "rem_u">;
|
||||
defm DIV_S : BinaryInt<sdiv, "div_s", 0x43, 0x5e>;
|
||||
defm DIV_U : BinaryInt<udiv, "div_u", 0x44, 0x5f>;
|
||||
defm REM_S : BinaryInt<srem, "rem_s", 0x45, 0x60>;
|
||||
defm REM_U : BinaryInt<urem, "rem_u", 0x46, 0x61>;
|
||||
} // hasSideEffects = 1
|
||||
let isCommutable = 1 in {
|
||||
defm AND : BinaryInt<and, "and ">;
|
||||
defm OR : BinaryInt<or, "or ">;
|
||||
defm XOR : BinaryInt<xor, "xor ">;
|
||||
defm AND : BinaryInt<and, "and ", 0x47, 0x62>;
|
||||
defm OR : BinaryInt<or, "or ", 0x48, 0x63>;
|
||||
defm XOR : BinaryInt<xor, "xor ", 0x49, 0x64>;
|
||||
} // isCommutable = 1
|
||||
defm SHL : BinaryInt<shl, "shl ">;
|
||||
defm SHR_U : BinaryInt<srl, "shr_u">;
|
||||
defm SHR_S : BinaryInt<sra, "shr_s">;
|
||||
defm ROTL : BinaryInt<rotl, "rotl">;
|
||||
defm ROTR : BinaryInt<rotr, "rotr">;
|
||||
defm SHL : BinaryInt<shl, "shl ", 0x4a, 0x65>;
|
||||
defm SHR_U : BinaryInt<srl, "shr_u", 0x4b, 0x66>;
|
||||
defm SHR_S : BinaryInt<sra, "shr_s", 0x4c, 0x67>;
|
||||
defm ROTL : BinaryInt<rotl, "rotl", 0xb7, 0xb9>;
|
||||
defm ROTR : BinaryInt<rotr, "rotr", 0xb6, 0xb8>;
|
||||
|
||||
let isCommutable = 1 in {
|
||||
defm EQ : ComparisonInt<SETEQ, "eq ">;
|
||||
defm NE : ComparisonInt<SETNE, "ne ">;
|
||||
defm EQ : ComparisonInt<SETEQ, "eq ", 0x4d, 0x68>;
|
||||
defm NE : ComparisonInt<SETNE, "ne ", 0x4e, 0x69>;
|
||||
} // isCommutable = 1
|
||||
defm LT_S : ComparisonInt<SETLT, "lt_s">;
|
||||
defm LE_S : ComparisonInt<SETLE, "le_s">;
|
||||
defm LT_U : ComparisonInt<SETULT, "lt_u">;
|
||||
defm LE_U : ComparisonInt<SETULE, "le_u">;
|
||||
defm GT_S : ComparisonInt<SETGT, "gt_s">;
|
||||
defm GE_S : ComparisonInt<SETGE, "ge_s">;
|
||||
defm GT_U : ComparisonInt<SETUGT, "gt_u">;
|
||||
defm GE_U : ComparisonInt<SETUGE, "ge_u">;
|
||||
defm LT_S : ComparisonInt<SETLT, "lt_s", 0x4f, 0x6a>;
|
||||
defm LE_S : ComparisonInt<SETLE, "le_s", 0x50, 0x6b>;
|
||||
defm LT_U : ComparisonInt<SETULT, "lt_u", 0x51, 0x6c>;
|
||||
defm LE_U : ComparisonInt<SETULE, "le_u", 0x52, 0x6d>;
|
||||
defm GT_S : ComparisonInt<SETGT, "gt_s", 0x53, 0x6e>;
|
||||
defm GE_S : ComparisonInt<SETGE, "ge_s", 0x54, 0x6f>;
|
||||
defm GT_U : ComparisonInt<SETUGT, "gt_u", 0x55, 0x70>;
|
||||
defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x56, 0x71>;
|
||||
|
||||
defm CLZ : UnaryInt<ctlz, "clz ">;
|
||||
defm CTZ : UnaryInt<cttz, "ctz ">;
|
||||
defm POPCNT : UnaryInt<ctpop, "popcnt">;
|
||||
defm CLZ : UnaryInt<ctlz, "clz ", 0x57, 0x72>;
|
||||
defm CTZ : UnaryInt<cttz, "ctz ", 0x58, 0x73>;
|
||||
defm POPCNT : UnaryInt<ctpop, "popcnt", 0x59, 0x74>;
|
||||
|
||||
def EQZ_I32 : I<(outs I32:$dst), (ins I32:$src),
|
||||
[(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
|
||||
"i32.eqz \t$dst, $src">;
|
||||
"i32.eqz \t$dst, $src", 0x5a>;
|
||||
def EQZ_I64 : I<(outs I32:$dst), (ins I64:$src),
|
||||
[(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
|
||||
"i64.eqz \t$dst, $src">;
|
||||
"i64.eqz \t$dst, $src", 0xba>;
|
||||
|
||||
} // Defs = [ARGUMENTS]
|
||||
|
||||
|
||||
@ -58,16 +58,16 @@ let Defs = [ARGUMENTS] in {
|
||||
// Basic load.
|
||||
def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i32.load\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>;
|
||||
def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>;
|
||||
def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"f32.load\t$dst, ${off}(${addr})${p2align}">;
|
||||
"f32.load\t$dst, ${off}(${addr})${p2align}", 0x2c>;
|
||||
def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"f64.load\t$dst, ${off}(${addr})${p2align}">;
|
||||
"f64.load\t$dst, ${off}(${addr})${p2align}", 0x2d>;
|
||||
|
||||
} // Defs = [ARGUMENTS]
|
||||
|
||||
@ -142,34 +142,34 @@ let Defs = [ARGUMENTS] in {
|
||||
// Extending load.
|
||||
def LOAD8_S_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i32.load8_s\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x20>;
|
||||
def LOAD8_U_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i32.load8_u\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x21>;
|
||||
def LOAD16_S_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i32.load16_s\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x22>;
|
||||
def LOAD16_U_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i32.load16_u\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x23>;
|
||||
def LOAD8_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load8_s\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x24>;
|
||||
def LOAD8_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load8_u\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x25>;
|
||||
def LOAD16_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load16_s\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x26>;
|
||||
def LOAD16_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load16_u\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x27>;
|
||||
def LOAD32_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load32_s\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x28>;
|
||||
def LOAD32_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align), [],
|
||||
"i64.load32_u\t$dst, ${off}(${addr})${p2align}">;
|
||||
"i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x29>;
|
||||
|
||||
} // Defs = [ARGUMENTS]
|
||||
|
||||
@ -453,16 +453,16 @@ let Defs = [ARGUMENTS] in {
|
||||
// Note: WebAssembly inverts SelectionDAG's usual operand order.
|
||||
def STORE_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I32:$val), [],
|
||||
"i32.store\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i32.store\t$dst, ${off}(${addr})${p2align}, $val", 0x33>;
|
||||
def STORE_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I64:$val), [],
|
||||
"i64.store\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i64.store\t$dst, ${off}(${addr})${p2align}, $val", 0x34>;
|
||||
def STORE_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, F32:$val), [],
|
||||
"f32.store\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"f32.store\t$dst, ${off}(${addr})${p2align}, $val", 0x35>;
|
||||
def STORE_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, F64:$val), [],
|
||||
"f64.store\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"f64.store\t$dst, ${off}(${addr})${p2align}, $val", 0x36>;
|
||||
|
||||
} // Defs = [ARGUMENTS]
|
||||
|
||||
@ -545,19 +545,19 @@ let Defs = [ARGUMENTS] in {
|
||||
// Truncating store.
|
||||
def STORE8_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I32:$val), [],
|
||||
"i32.store8\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i32.store8\t$dst, ${off}(${addr})${p2align}, $val", 0x2e>;
|
||||
def STORE16_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I32:$val), [],
|
||||
"i32.store16\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i32.store16\t$dst, ${off}(${addr})${p2align}, $val", 0x2f>;
|
||||
def STORE8_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I64:$val), [],
|
||||
"i64.store8\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i64.store8\t$dst, ${off}(${addr})${p2align}, $val", 0x30>;
|
||||
def STORE16_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I64:$val), [],
|
||||
"i64.store16\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i64.store16\t$dst, ${off}(${addr})${p2align}, $val", 0x31>;
|
||||
def STORE32_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
|
||||
P2Align:$p2align, I64:$val), [],
|
||||
"i64.store32\t$dst, ${off}(${addr})${p2align}, $val">;
|
||||
"i64.store32\t$dst, ${off}(${addr})${p2align}, $val", 0x32>;
|
||||
|
||||
} // Defs = [ARGUMENTS]
|
||||
|
||||
@ -671,7 +671,7 @@ let Defs = [ARGUMENTS] in {
|
||||
// Current memory size.
|
||||
def CURRENT_MEMORY_I32 : I<(outs I32:$dst), (ins),
|
||||
[(set I32:$dst, (int_wasm_current_memory))],
|
||||
"current_memory\t$dst">,
|
||||
"current_memory\t$dst", 0x3b>,
|
||||
Requires<[HasAddr32]>;
|
||||
def CURRENT_MEMORY_I64 : I<(outs I64:$dst), (ins),
|
||||
[(set I64:$dst, (int_wasm_current_memory))],
|
||||
@ -681,7 +681,7 @@ def CURRENT_MEMORY_I64 : I<(outs I64:$dst), (ins),
|
||||
// Grow memory.
|
||||
def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
|
||||
[(int_wasm_grow_memory I32:$delta)],
|
||||
"grow_memory\t$delta">,
|
||||
"grow_memory\t$delta", 0x39>,
|
||||
Requires<[HasAddr32]>;
|
||||
def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
|
||||
[(int_wasm_grow_memory I64:$delta)],
|
||||
|
||||
Loading…
Reference in New Issue
Block a user