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- Add AVX form of all SSE2 logical instructions
- Add VEX encoding bits to x86 MRM0r-MRM7r llvm-svn: 107238
This commit is contained in:
Bruno Cardoso Lopes
parent
00ee7ba38c
commit
cfbebb3921
@ -2440,6 +2440,68 @@ defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw>;
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// SSE2 - Packed Integer Logical Instructions
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//===---------------------------------------------------------------------===//
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
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defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
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int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
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VEX_4V;
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defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
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int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
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VEX_4V;
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defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
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int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
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VEX_4V;
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defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
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int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
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VEX_4V;
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defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
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int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
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VEX_4V;
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defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
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int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
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VEX_4V;
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defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
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int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
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VEX_4V;
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defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
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int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
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VEX_4V;
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let isCommutable = 1 in {
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defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 0>, VEX_4V;
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defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 0>, VEX_4V;
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defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 0>, VEX_4V;
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}
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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// 128-bit logical shifts.
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def VPSLLDQri : PDIi8<0x73, MRM7r,
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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"vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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VEX_4V;
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def VPSRLDQri : PDIi8<0x73, MRM3r,
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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"vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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VEX_4V;
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// PSRADQri doesn't exist in SSE[1-3].
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}
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def VPANDNrr : PDI<0xDF, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
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VR128:$src2)))]>, VEX_4V;
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def VPANDNrm : PDI<0xDF, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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"vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
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(memopv2i64 addr:$src2))))]>,
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VEX_4V;
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}
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}
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let Constraints = "$src1 = $dst" in {
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defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
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int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
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@ -60,6 +60,27 @@ public:
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static unsigned GetX86RegNum(const MCOperand &MO) {
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return X86RegisterInfo::getX86RegNum(MO.getReg());
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}
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// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
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// 0-7 and the difference between the 2 groups is given by the REX prefix.
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// In the VEX prefix, registers are seen sequencially from 0-15 and encoded
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// in 1's complement form, example:
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//
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// ModRM field => XMM9 => 1
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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static unsigned char getVEXRegisterEncoding(const MCInst &MI,
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unsigned OpNum) {
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unsigned SrcReg = MI.getOperand(OpNum).getReg();
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unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
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if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
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SrcRegNum += 8;
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// The registers represented through VEX_VVVV should
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// be encoded in 1's complement form.
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return (~SrcRegNum) & 0xf;
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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@ -134,7 +155,6 @@ MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
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return new X86MCCodeEmitter(TM, Ctx, true);
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}
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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@ -469,29 +489,12 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_R = 0x0;
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// If the memory destination has been checked first,
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// go back to the first operand
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// CurOp and NumOps are equal when VEX_R represents a register used
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// to index a memory destination (which is the last operand)
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CurOp = (CurOp == NumOps) ? 0 : CurOp+1;
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// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the
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// range 0-7 and the difference between the 2 groups is given by the
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// REX prefix. In the VEX prefix, registers are seen sequencially
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// from 0-15 and encoded in 1's complement form, example:
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//
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// ModRM field => XMM9 => 1
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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if (HasVEX_4V) {
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unsigned SrcReg = MI.getOperand(CurOp).getReg();
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unsigned SrcRegNum = GetX86RegNum(MI.getOperand(1));
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if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
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SrcRegNum += 8;
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// The registers represented through VEX_VVVV should
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// be encoded in 1's complement form.
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VEX_4V = (~SrcRegNum) & 0xf;
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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CurOp++;
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}
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@ -505,7 +508,17 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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VEX_X = 0x0;
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}
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break;
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default:
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default: // MRM0r-MRM7r
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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CurOp++;
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for (; CurOp != NumOps; ++CurOp) {
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const MCOperand &MO = MI.getOperand(CurOp);
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if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
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VEX_B = 0x0;
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}
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break;
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assert(0 && "Not implemented!");
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}
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@ -831,6 +844,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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case X86II::MRM2r: case X86II::MRM3r:
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case X86II::MRM4r: case X86II::MRM5r:
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case X86II::MRM6r: case X86II::MRM7r:
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if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
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CurOp++;
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EmitByte(BaseOpcode, CurByte, OS);
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EmitRegModRMByte(MI.getOperand(CurOp++),
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(TSFlags & X86II::FormMask)-X86II::MRM0r,
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@ -11182,3 +11182,143 @@
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// CHECK: encoding: [0xc5,0xe9,0xf6,0x18]
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vpsadbw (%eax), %xmm2, %xmm3
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// CHECK: vpsllw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xf1,0xd9]
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vpsllw %xmm1, %xmm2, %xmm3
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// CHECK: vpsllw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xf1,0x18]
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vpsllw (%eax), %xmm2, %xmm3
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// CHECK: vpslld %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xf2,0xd9]
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vpslld %xmm1, %xmm2, %xmm3
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// CHECK: vpslld (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xf2,0x18]
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vpslld (%eax), %xmm2, %xmm3
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// CHECK: vpsllq %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xf3,0xd9]
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vpsllq %xmm1, %xmm2, %xmm3
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// CHECK: vpsllq (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xf3,0x18]
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vpsllq (%eax), %xmm2, %xmm3
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// CHECK: vpsraw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xe1,0xd9]
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vpsraw %xmm1, %xmm2, %xmm3
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// CHECK: vpsraw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xe1,0x18]
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vpsraw (%eax), %xmm2, %xmm3
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// CHECK: vpsrad %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xe2,0xd9]
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vpsrad %xmm1, %xmm2, %xmm3
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// CHECK: vpsrad (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xe2,0x18]
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vpsrad (%eax), %xmm2, %xmm3
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// CHECK: vpsrlw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xd1,0xd9]
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vpsrlw %xmm1, %xmm2, %xmm3
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// CHECK: vpsrlw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xd1,0x18]
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vpsrlw (%eax), %xmm2, %xmm3
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// CHECK: vpsrld %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xd2,0xd9]
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vpsrld %xmm1, %xmm2, %xmm3
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// CHECK: vpsrld (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xd2,0x18]
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vpsrld (%eax), %xmm2, %xmm3
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// CHECK: vpsrlq %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xd3,0xd9]
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vpsrlq %xmm1, %xmm2, %xmm3
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// CHECK: vpsrlq (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xd3,0x18]
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vpsrlq (%eax), %xmm2, %xmm3
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// CHECK: vpslld $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a]
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vpslld $10, %xmm2, %xmm3
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// CHECK: vpslldq $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x73,0xfa,0x0a]
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vpslldq $10, %xmm2, %xmm3
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// CHECK: vpsllq $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x73,0xf2,0x0a]
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vpsllq $10, %xmm2, %xmm3
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// CHECK: vpsllw $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x71,0xf2,0x0a]
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vpsllw $10, %xmm2, %xmm3
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// CHECK: vpsrad $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x72,0xe2,0x0a]
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vpsrad $10, %xmm2, %xmm3
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// CHECK: vpsraw $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x71,0xe2,0x0a]
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vpsraw $10, %xmm2, %xmm3
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// CHECK: vpsrld $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x72,0xd2,0x0a]
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vpsrld $10, %xmm2, %xmm3
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// CHECK: vpsrldq $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x73,0xda,0x0a]
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vpsrldq $10, %xmm2, %xmm3
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// CHECK: vpsrlq $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x73,0xd2,0x0a]
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vpsrlq $10, %xmm2, %xmm3
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// CHECK: vpsrlw $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x71,0xd2,0x0a]
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vpsrlw $10, %xmm2, %xmm3
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// CHECK: vpslld $10, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a]
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vpslld $10, %xmm2, %xmm3
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// CHECK: vpand %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xdb,0xd9]
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vpand %xmm1, %xmm2, %xmm3
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// CHECK: vpand (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xdb,0x18]
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vpand (%eax), %xmm2, %xmm3
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// CHECK: vpor %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xeb,0xd9]
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vpor %xmm1, %xmm2, %xmm3
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// CHECK: vpor (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xeb,0x18]
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vpor (%eax), %xmm2, %xmm3
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// CHECK: vpxor %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xef,0xd9]
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vpxor %xmm1, %xmm2, %xmm3
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// CHECK: vpxor (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xef,0x18]
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vpxor (%eax), %xmm2, %xmm3
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// CHECK: vpandn %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xdf,0xd9]
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vpandn %xmm1, %xmm2, %xmm3
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// CHECK: vpandn (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xdf,0x18]
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vpandn (%eax), %xmm2, %xmm3
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@ -1222,3 +1222,143 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc5,0x19,0xf6,0x28]
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vpsadbw (%rax), %xmm12, %xmm13
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// CHECK: vpsllw %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x19,0xf1,0xeb]
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vpsllw %xmm11, %xmm12, %xmm13
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// CHECK: vpsllw (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x19,0xf1,0x28]
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vpsllw (%rax), %xmm12, %xmm13
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// CHECK: vpslld %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x19,0xf2,0xeb]
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vpslld %xmm11, %xmm12, %xmm13
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// CHECK: vpslld (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x19,0xf2,0x28]
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vpslld (%rax), %xmm12, %xmm13
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// CHECK: vpsllq %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x19,0xf3,0xeb]
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vpsllq %xmm11, %xmm12, %xmm13
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// CHECK: vpsllq (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x19,0xf3,0x28]
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vpsllq (%rax), %xmm12, %xmm13
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// CHECK: vpsraw %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x19,0xe1,0xeb]
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vpsraw %xmm11, %xmm12, %xmm13
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// CHECK: vpsraw (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x19,0xe1,0x28]
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vpsraw (%rax), %xmm12, %xmm13
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// CHECK: vpsrad %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x19,0xe2,0xeb]
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vpsrad %xmm11, %xmm12, %xmm13
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// CHECK: vpsrad (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x19,0xe2,0x28]
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vpsrad (%rax), %xmm12, %xmm13
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|
||||
// CHECK: vpsrlw %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xd1,0xeb]
|
||||
vpsrlw %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrlw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xd1,0x28]
|
||||
vpsrlw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrld %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xd2,0xeb]
|
||||
vpsrld %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrld (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xd2,0x28]
|
||||
vpsrld (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrlq %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xd3,0xeb]
|
||||
vpsrlq %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrlq (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xd3,0x28]
|
||||
vpsrlq (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpslld $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a]
|
||||
vpslld $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpslldq $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xfc,0x0a]
|
||||
vpslldq $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsllq $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xf4,0x0a]
|
||||
vpsllq $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsllw $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xf4,0x0a]
|
||||
vpsllw $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrad $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xe4,0x0a]
|
||||
vpsrad $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsraw $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xe4,0x0a]
|
||||
vpsraw $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrld $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xd4,0x0a]
|
||||
vpsrld $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrldq $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xdc,0x0a]
|
||||
vpsrldq $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrlq $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xd4,0x0a]
|
||||
vpsrlq $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsrlw $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xd4,0x0a]
|
||||
vpsrlw $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpslld $10, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a]
|
||||
vpslld $10, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpand %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xdb,0xeb]
|
||||
vpand %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpand (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xdb,0x28]
|
||||
vpand (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpor %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xeb,0xeb]
|
||||
vpor %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpor (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xeb,0x28]
|
||||
vpor (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpxor %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xef,0xeb]
|
||||
vpxor %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpxor (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xef,0x28]
|
||||
vpxor (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpandn %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x41,0x19,0xdf,0xeb]
|
||||
vpandn %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpandn (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc5,0x19,0xdf,0x28]
|
||||
vpandn (%rax), %xmm12, %xmm13
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user