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Add MVT::is128BitVector and is64BitVector. Shrink

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unaligned load/store code using them.  Per review
of unaligned load/store vector patch.

llvm-svn: 47782
This commit is contained in:
Dale Johannesen 2008-03-01 03:40:57 +00:00
parent 1ce9ac19d3
commit cfd005f2ea
2 changed files with 18 additions and 16 deletions
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13
include/llvm/CodeGen/ValueTypes.h
View File

@ -250,6 +250,19 @@ namespace MVT { // MVT = Machine Value Types
return (getSizeInBits(VT) + 7)/8*8; return (getSizeInBits(VT) + 7)/8*8;
} }
/// MVT::is64BitVector - Return true if this is a 64-bit vector type.
static inline bool is64BitVector(ValueType VT) {
return (VT==v8i8 || VT==v4i16 || VT==v2i32 || VT==v1i64 || VT==v2f32 ||
(isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==64));
}
/// MVT::is128BitVector - Return true if this is a 128-bit vector type.
static inline bool is128BitVector(ValueType VT) {
return (VT==v16i8 || VT==v8i16 || VT==v4i32 || VT==v2i64 ||
VT==v4f32 || VT==v2f64 ||
(isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==128));
}
/// MVT::getIntegerType - Returns the ValueType that represents an integer /// MVT::getIntegerType - Returns the ValueType that represents an integer
/// with the given number of bits. /// with the given number of bits.
/// ///

21
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -574,15 +574,9 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
// Expand to a bitconvert of the value to the integer type of the // Expand to a bitconvert of the value to the integer type of the
// same size, then a (misaligned) int store. // same size, then a (misaligned) int store.
MVT::ValueType intVT; MVT::ValueType intVT;
if (VT == MVT::v8i16 || VT == MVT::v4i32 || if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
VT == MVT::v2i64 || VT == MVT::v2f64 ||
VT == MVT::v4f32 || VT == MVT::v16i8 ||
VT == MVT::ppcf128)
intVT = MVT::i128; intVT = MVT::i128;
else if (VT==MVT::f64 || else if (MVT::is64BitVector(VT) || VT==MVT::f64)
VT == MVT::v8i8 || VT == MVT::v4i16 ||
VT == MVT::v2i32 || VT == MVT::v1i64 ||
VT == MVT::v2f32)
intVT = MVT::i64; intVT = MVT::i64;
else if (VT==MVT::f32) else if (VT==MVT::f32)
intVT = MVT::i32; intVT = MVT::i32;
@ -634,15 +628,10 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
// Expand to a (misaligned) integer load of the same size, // Expand to a (misaligned) integer load of the same size,
// then bitconvert to floating point or vector. // then bitconvert to floating point or vector.
MVT::ValueType intVT; MVT::ValueType intVT;
if (LoadedVT == MVT::v8i16 || LoadedVT == MVT::v4i32 || if (MVT::is128BitVector(LoadedVT) ||
LoadedVT == MVT::v2i64 || LoadedVT == MVT::v2f64 || LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
LoadedVT == MVT::v4f32 || LoadedVT == MVT::v16i8 ||
LoadedVT == MVT::ppcf128)
intVT = MVT::i128; intVT = MVT::i128;
else if (LoadedVT == MVT::f64 || else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
LoadedVT == MVT::v8i8 || LoadedVT == MVT::v4i16 ||
LoadedVT == MVT::v2i32 || LoadedVT == MVT::v1i64 ||
LoadedVT == MVT::v2f32)
intVT = MVT::i64; intVT = MVT::i64;
else if (LoadedVT == MVT::f32) else if (LoadedVT == MVT::f32)
intVT = MVT::i32; intVT = MVT::i32;