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- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
splat and PSHUFD cases. - Clean up shuffle / splat matching code. llvm-svn: 26954
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@ -1368,6 +1368,26 @@ static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) {
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(GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
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(GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
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}
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}
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool X86::isPSHUFDMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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if (N->getNumOperands() != 4)
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return false;
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// Check if the value doesn't reference the second vector.
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SDOperand Elt = N->getOperand(0);
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assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
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for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4) return false;
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}
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return true;
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}
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
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/// a splat of a single element.
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/// a splat of a single element.
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bool X86::isSplatMask(SDNode *N) {
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bool X86::isSplatMask(SDNode *N) {
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@ -2211,17 +2231,26 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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SDOperand PermMask = Op.getOperand(2);
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SDOperand PermMask = Op.getOperand(2);
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType VT = Op.getValueType();
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if (V2.getOpcode() == ISD::UNDEF) {
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// Handle splat cases.
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// Handle splat cases.
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if (X86::isSplatMask(PermMask.Val)) {
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if (X86::isSplatMask(PermMask.Val)) {
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if (V2.getOpcode() == ISD::UNDEF)
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if (VT == MVT::v2f64 || VT == MVT::v2i64)
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// Use unpcklpd
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return DAG.getNode(X86ISD::UNPCKLP, VT, V1, V1);
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// Leave the VECTOR_SHUFFLE alone. It matches SHUFP*.
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// Leave the VECTOR_SHUFFLE alone. It matches SHUFP*.
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return SDOperand();
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return SDOperand();
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} else if (VT == MVT::v4f32)
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else
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// Make it match SHUFP* or UNPCKLPD. Second vector is undef since it's
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// not needed.
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),
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PermMask);
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} else if (X86::isPSHUFDMask(PermMask.Val)) {
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if (V2.getOpcode() == ISD::UNDEF)
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// Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
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// Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
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return SDOperand();
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return SDOperand();
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else
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// Make it match PSHUFD. Second vector is undef since it's not needed.
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),
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PermMask);
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}
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}
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// TODO.
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// TODO.
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@ -2262,7 +2291,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
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case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
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case X86ISD::Wrapper: return "X86ISD::Wrapper";
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case X86ISD::Wrapper: return "X86ISD::Wrapper";
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case X86ISD::SCALAR_TO_VECTOR: return "X86ISD::SCALAR_TO_VECTOR";
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case X86ISD::SCALAR_TO_VECTOR: return "X86ISD::SCALAR_TO_VECTOR";
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case X86ISD::UNPCKLP: return "X86ISD::UNPCKLP";
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}
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}
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}
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}
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@ -2341,3 +2369,11 @@ bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
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} else
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} else
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return true;
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return true;
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}
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}
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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bool X86TargetLowering::isShuffleMaskLegal(SDOperand Mask) const {
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return (X86::isSplatMask(Mask.Val) || X86::isPSHUFDMask(Mask.Val));
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}
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@ -179,6 +179,10 @@ namespace llvm {
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/// Define some predicates that are used for node matching.
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/// Define some predicates that are used for node matching.
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namespace X86 {
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namespace X86 {
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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bool isSplatMask(SDNode *N);
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@ -259,6 +263,11 @@ namespace llvm {
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virtual bool isLegalAddressImmediate(int64_t V) const;
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virtual bool isLegalAddressImmediate(int64_t V) const;
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virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
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virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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virtual bool isShuffleMaskLegal(SDOperand Mask) const;
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private:
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private:
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// C Calling Convention implementation.
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// C Calling Convention implementation.
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std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
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std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
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@ -55,7 +55,15 @@ def SHUFP_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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return X86::isSplatMask(N);
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}], SHUFFLE_get_shuf_imm>;
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}], SHUFFLE_get_shuf_imm>;
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def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{}], SHUFFLE_get_pshufd_imm>;
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def UNPCKLP_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}]>;
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// Only use PSHUF if it is not a splat.
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def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
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return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
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}], SHUFFLE_get_pshufd_imm>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SSE scalar FP Instructions
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// SSE scalar FP Instructions
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@ -691,9 +699,7 @@ def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrr : PDIi8<0x70, MRMDestReg,
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def PSHUFDrr : PDIi8<0x70, MRMDestReg,
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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[(set VR128:$dst, (vector_shuffle (v4f32 VR128:$src1), (undef),
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PSHUFD_shuffle_mask:$src2))]>;
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def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
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def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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@ -809,12 +815,13 @@ def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
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(v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>;
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(v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>;
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// Splat v2f64 / v2i64
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// Splat v2f64 / v2i64
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def : Pat<(X86unpcklp (v2f64 VR128:$src1), VR128:$src2),
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def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKLP_splat_mask:$sm),
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(v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>;
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(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>;
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def : Pat<(X86unpcklp (v2i64 VR128:$src1), VR128:$src2),
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def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKLP_splat_mask:$sm),
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(v2i64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>;
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(v2i64 (UNPCKLPDrr VR128:$src, VR128:$src))>;
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// Shuffle v4i32, undef
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// Shuffle v4f32 / v4i32, undef. These should only match if splat cases do not.
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def : Pat<(vector_shuffle (v4i32 VR128:$src1), (undef),
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def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
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PSHUFD_shuffle_mask:$src2),
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(v4f32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>;
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(v4i32 (PSHUFDrr VR128:$src1, PSHUFD_shuffle_mask:$src2))>;
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def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
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(v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>;
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