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[Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends.

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llvm-svn: 226210
This commit is contained in:
Colin LeMahieu 2015-01-15 21:35:49 +00:00
parent dcf8b14857
commit d02bf117bc
2 changed files with 14 additions and 61 deletions
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31
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -1567,9 +1567,9 @@ let AddedComplexity = 20 in {
defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
//defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
//defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
@ -1703,33 +1703,6 @@ defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
(i32 (L2_loadrb_io AddrFI:$addr, 0)) >;
// Load byte any-extend.
def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
(i32 (L2_loadrb_io AddrFI:$addr, 0)) >;
// Indexed load byte any-extend.
let AddedComplexity = 20 in
def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
(i32 (L2_loadrb_io IntRegs:$src1, s11_0ImmPred:$offset)) >;
def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
(i32 (L2_loadrh_io AddrFI:$addr, 0))>;
let AddedComplexity = 20 in
def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
(i32 (L2_loadrh_io IntRegs:$src1, s11_1ImmPred:$offset)) >;
let AddedComplexity = 10 in
def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
(i32 (L2_loadrub_io AddrFI:$addr, 0))>;
let AddedComplexity = 20 in
def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
(i32 (L2_loadrub_io IntRegs:$src1, s11_0ImmPred:$offset))>;
//===----------------------------------------------------------------------===//
// Template class for post increment loads with register offset.
//===----------------------------------------------------------------------===//

44
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -501,41 +501,21 @@ def : Pat <(i64 (load (add IntRegs:$src1,
Requires<[HasV4T]>;
}
// 'def pats' for load instruction base + register offset and
// zero immediate value.
let AddedComplexity = 10 in {
def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
: Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
(VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
(L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
Requires<[HasV4T]>;
let AddedComplexity = 20 in {
def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
}
// zext i1->i64