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Change isUIntN/isIntN calls with constant N to use the template version. NFC

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llvm-svn: 249952
This commit is contained in:
Craig Topper 2015-10-10 20:17:07 +00:00
parent ce9ae99d64
commit d0338c475c
3 changed files with 14 additions and 14 deletions
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2
lib/MC/MCParser/AsmParser.cpp
View File

@ -4488,7 +4488,7 @@ bool AsmParser::parseDirectiveMSEmit(SMLoc IDLoc, ParseStatementInfo &Info,
if (!MCE)
return Error(ExprLoc, "unexpected expression in _emit");
uint64_t IntValue = MCE->getValue();
if (!isUIntN(8, IntValue) && !isIntN(8, IntValue))
if (!isUInt<8>(IntValue) && !isInt<8>(IntValue))
return Error(ExprLoc, "literal value out of range for directive");
Info.AsmRewrites->emplace_back(AOK_Emit, IDLoc, Len);

10
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -1441,7 +1441,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
Offset = Inst.getOperand(1);
if (!Offset.isImm())
break; // We'll deal with this situation later on when applying fixups.
if (!isIntN(8, Offset.getImm()))
if (!isInt<8>(Offset.getImm()))
return Error(IDLoc, "branch target out of range");
if (OffsetToAlignment(Offset.getImm(), 2LL))
return Error(IDLoc, "branch to misaligned address");
@ -1663,7 +1663,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
int MemOffset = Op.getImm();
MCOperand &DstReg = Inst.getOperand(0);
MCOperand &BaseReg = Inst.getOperand(1);
if (isIntN(9, MemOffset) && (MemOffset % 4 == 0) &&
if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
getContext().getRegisterInfo()->getRegClass(
Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
(BaseReg.getReg() == Mips::GP ||
@ -1808,7 +1808,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind");
int Imm = Opnd.getImm();
if ((Imm % 4 != 0) || !isIntN(25, Imm))
if ((Imm % 4 != 0) || !isInt<25>(Imm))
return Error(IDLoc, "immediate operand value out of range");
break;
}
@ -2461,13 +2461,13 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(
Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
} else {
assert(Offset.isImm() && "expected immediate operand kind");
if (isIntN(11, Offset.getImm())) {
if (isInt<11>(Offset.getImm())) {
// If offset fits into 11 bits then this instruction becomes microMIPS
// 16-bit unconditional branch instruction.
if (inMicroMipsMode())
Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
} else {
if (!isIntN(17, Offset.getImm()))
if (!isInt<17>(Offset.getImm()))
Error(IDLoc, "branch target out of range");
if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
Error(IDLoc, "branch to misaligned address");

16
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
View File

@ -63,14 +63,14 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
// address range. Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 4;
// We now check if Value can be encoded as a 16-bit signed immediate.
if (!isIntN(16, Value) && Ctx)
if (!isInt<16>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC16 fixup");
break;
case Mips::fixup_MIPS_PC19_S2:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 4;
// We now check if Value can be encoded as a 19-bit signed immediate.
if (!isIntN(19, Value) && Ctx)
if (!isInt<19>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC19 fixup");
break;
case Mips::fixup_Mips_26:
@ -104,7 +104,7 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 2;
// We now check if Value can be encoded as a 7-bit signed immediate.
if (!isIntN(7, Value) && Ctx)
if (!isInt<7>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC7 fixup");
break;
case Mips::fixup_MICROMIPS_PC10_S1:
@ -112,7 +112,7 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 2;
// We now check if Value can be encoded as a 10-bit signed immediate.
if (!isIntN(10, Value) && Ctx)
if (!isInt<10>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC10 fixup");
break;
case Mips::fixup_MICROMIPS_PC16_S1:
@ -120,28 +120,28 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 2;
// We now check if Value can be encoded as a 16-bit signed immediate.
if (!isIntN(16, Value) && Ctx)
if (!isInt<16>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC16 fixup");
break;
case Mips::fixup_MIPS_PC18_S3:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 8;
// We now check if Value can be encoded as a 18-bit signed immediate.
if (!isIntN(18, Value) && Ctx)
if (!isInt<18>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC18 fixup");
break;
case Mips::fixup_MIPS_PC21_S2:
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 4;
// We now check if Value can be encoded as a 21-bit signed immediate.
if (!isIntN(21, Value) && Ctx)
if (!isInt<21>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC21 fixup");
break;
case Mips::fixup_MIPS_PC26_S2:
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 4;
// We now check if Value can be encoded as a 26-bit signed immediate.
if (!isIntN(26, Value) && Ctx)
if (!isInt<26>(Value) && Ctx)
Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
break;
}