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pre-RA-sched: Cleanup register pressure tracking.

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Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.

llvm-svn: 133917
This commit is contained in:
Andrew Trick 2011-06-27 18:01:20 +00:00
parent 58c34c0e80
commit d0cdcee532
2 changed files with 4 additions and 16 deletions
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10
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -2029,13 +2029,9 @@ void RegReductionPQBase::UnscheduledNode(SUnit *SU) {
unsigned POpc = PN->getMachineOpcode();
if (POpc == TargetOpcode::IMPLICIT_DEF)
continue;
if (POpc == TargetOpcode::EXTRACT_SUBREG) {
EVT VT = PN->getOperand(0).getValueType();
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
continue;
} else if (POpc == TargetOpcode::INSERT_SUBREG ||
POpc == TargetOpcode::SUBREG_TO_REG) {
if (POpc == TargetOpcode::EXTRACT_SUBREG ||
POpc == TargetOpcode::INSERT_SUBREG ||
POpc == TargetOpcode::SUBREG_TO_REG) {
EVT VT = PN->getValueType(0);
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);

10
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -520,15 +520,7 @@ void ScheduleDAGSDNodes::RegDefIter::Advance() {
for (;DefIdx < NodeNumDefs; ++DefIdx) {
if (!Node->hasAnyUseOfValue(DefIdx))
continue;
if (Node->isMachineOpcode() &&
Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG &&
Node->getOperand(0).getValueType() != MVT::untyped) {
// Propagate the incoming (full-register) type. I doubt it's needed.
ValueType = Node->getOperand(0).getValueType();
}
else {
ValueType = Node->getValueType(DefIdx);
}
ValueType = Node->getValueType(DefIdx);
++DefIdx;
return; // Found a normal regdef.
}