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[AArch64][GlobalISel] Enable some select combines after legalization.
The legalizer generates selects for some operations, which can have constant condition values, resulting in lots of dead code if it's not folded away. Differential Revision: https://reviews.llvm.org/D106762
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Amara Emerson
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@ -203,6 +203,7 @@ def AArch64PostLegalizerCombinerHelper
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extractvecelt_pairwise_add, redundant_or,
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mul_const, redundant_sext_inreg,
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form_bitfield_extract, rotate_out_of_range,
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icmp_to_true_false_known_bits, merge_unmerge]> {
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icmp_to_true_false_known_bits, merge_unmerge,
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select_combines]> {
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let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
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}
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@ -351,27 +351,14 @@ define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) {
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; CHECK-LLSC-O1-NEXT: sub x9, x8, #64 // =64
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; CHECK-LLSC-O1-NEXT: .LBB4_1: // %atomicrmw.start
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; CHECK-LLSC-O1-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-LLSC-O1-NEXT: ldxp x11, x10, [x2]
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; CHECK-LLSC-O1-NEXT: sub x12, x8, #64 // =64
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; CHECK-LLSC-O1-NEXT: tst wzr, #0x1
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; CHECK-LLSC-O1-NEXT: lsl x13, x10, x8
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; CHECK-LLSC-O1-NEXT: lsr x14, x10, x9
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; CHECK-LLSC-O1-NEXT: lsl x10, x10, x12
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; CHECK-LLSC-O1-NEXT: csel x10, x14, x10, ne
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; CHECK-LLSC-O1-NEXT: csel x13, x13, xzr, ne
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; CHECK-LLSC-O1-NEXT: csel x10, xzr, x10, ne
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; CHECK-LLSC-O1-NEXT: orr x11, x11, x13
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; CHECK-LLSC-O1-NEXT: lsl x13, x10, x9
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; CHECK-LLSC-O1-NEXT: lsr x12, x10, x12
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; CHECK-LLSC-O1-NEXT: orr x13, x13, x11, lsr #0
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; CHECK-LLSC-O1-NEXT: tst wzr, #0x1
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; CHECK-LLSC-O1-NEXT: csel x12, x13, x12, ne
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; CHECK-LLSC-O1-NEXT: csel x12, x11, x12, ne
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; CHECK-LLSC-O1-NEXT: stxp w13, x11, x12, [x2]
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; CHECK-LLSC-O1-NEXT: cbnz w13, .LBB4_1
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; CHECK-LLSC-O1-NEXT: ldxp x10, x8, [x2]
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; CHECK-LLSC-O1-NEXT: lsl x8, x8, x9
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; CHECK-LLSC-O1-NEXT: lsr x11, x8, x9
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; CHECK-LLSC-O1-NEXT: stxp w12, x10, x11, [x2]
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; CHECK-LLSC-O1-NEXT: cbnz w12, .LBB4_1
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; CHECK-LLSC-O1-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-LLSC-O1-NEXT: mov v0.d[0], x11
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; CHECK-LLSC-O1-NEXT: mov v0.d[1], x10
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; CHECK-LLSC-O1-NEXT: mov v0.d[0], x10
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; CHECK-LLSC-O1-NEXT: mov v0.d[1], x8
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; CHECK-LLSC-O1-NEXT: str q0, [x3]
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; CHECK-LLSC-O1-NEXT: ret
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;
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@ -381,27 +368,14 @@ define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) {
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; CHECK-CAS-O1-NEXT: sub x9, x8, #64 // =64
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; CHECK-CAS-O1-NEXT: .LBB4_1: // %atomicrmw.start
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; CHECK-CAS-O1-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-CAS-O1-NEXT: ldxp x11, x10, [x2]
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; CHECK-CAS-O1-NEXT: sub x12, x8, #64 // =64
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; CHECK-CAS-O1-NEXT: lsl x13, x10, x8
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; CHECK-CAS-O1-NEXT: lsr x14, x10, x9
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; CHECK-CAS-O1-NEXT: lsl x10, x10, x12
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; CHECK-CAS-O1-NEXT: tst wzr, #0x1
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; CHECK-CAS-O1-NEXT: csel x13, x13, xzr, ne
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; CHECK-CAS-O1-NEXT: csel x10, x14, x10, ne
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; CHECK-CAS-O1-NEXT: csel x10, xzr, x10, ne
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; CHECK-CAS-O1-NEXT: orr x11, x11, x13
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; CHECK-CAS-O1-NEXT: lsl x13, x10, x9
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; CHECK-CAS-O1-NEXT: orr x13, x13, x11, lsr #0
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; CHECK-CAS-O1-NEXT: lsr x12, x10, x12
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; CHECK-CAS-O1-NEXT: tst wzr, #0x1
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; CHECK-CAS-O1-NEXT: csel x12, x13, x12, ne
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; CHECK-CAS-O1-NEXT: csel x12, x11, x12, ne
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; CHECK-CAS-O1-NEXT: stxp w13, x11, x12, [x2]
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; CHECK-CAS-O1-NEXT: cbnz w13, .LBB4_1
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; CHECK-CAS-O1-NEXT: ldxp x10, x8, [x2]
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; CHECK-CAS-O1-NEXT: lsl x8, x8, x9
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; CHECK-CAS-O1-NEXT: lsr x11, x8, x9
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; CHECK-CAS-O1-NEXT: stxp w12, x10, x11, [x2]
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; CHECK-CAS-O1-NEXT: cbnz w12, .LBB4_1
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; CHECK-CAS-O1-NEXT: // %bb.2: // %atomicrmw.end
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; CHECK-CAS-O1-NEXT: mov v0.d[0], x11
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; CHECK-CAS-O1-NEXT: mov v0.d[1], x10
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; CHECK-CAS-O1-NEXT: mov v0.d[0], x10
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; CHECK-CAS-O1-NEXT: mov v0.d[1], x8
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; CHECK-CAS-O1-NEXT: str q0, [x3]
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; CHECK-CAS-O1-NEXT: ret
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;
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@ -0,0 +1,67 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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---
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# select (c, x, x) -> x
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name: test_combine_select_same_res
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legalized: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: test_combine_select_same_res
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
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; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
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; CHECK: $x0 = COPY [[SELECT]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s1) = G_TRUNC %0
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%2:_(s64) = G_SELECT %1, %0, %0
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$x0 = COPY %2(s64)
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...
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---
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# select (undef, x, y) -> y
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name: test_combine_select_undef_res0_res1
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legalized: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: test_combine_select_undef_res0_res1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: $x0 = COPY [[COPY]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s1) = G_IMPLICIT_DEF
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%3:_(s64) = G_SELECT %2, %0, %1
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$x0 = COPY %3(s64)
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...
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---
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# select (false, x, y) -> y
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name: test_combine_select_false_res0_res1
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legalized: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: test_combine_select_false_res0_res1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: $x0 = COPY [[COPY]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s1) = G_CONSTANT i1 false
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%3:_(s64) = G_SELECT %2, %0, %1
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$x0 = COPY %3(s64)
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...
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---
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# select (true, x, y) -> x
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name: test_combine_select_true_res0_res1
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legalized: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: test_combine_select_true_res0_res1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: $x0 = COPY [[COPY]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s1) = G_CONSTANT i1 true
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%3:_(s64) = G_SELECT %2, %0, %1
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$x0 = COPY %3(s64)
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...
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@ -132,16 +132,10 @@ define i32 @f7() {
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; GISEL-NEXT: add x8, x8, :lo12:x3+88
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; GISEL-NEXT: mov v0.d[1], x8
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; GISEL-NEXT: mov w9, #64
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; GISEL-NEXT: mov d1, v0.d[1]
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; GISEL-NEXT: mov d0, v0.d[1]
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; GISEL-NEXT: sub x8, x9, #64 // =64
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; GISEL-NEXT: fmov x10, d1
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; GISEL-NEXT: fmov x9, d0
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; GISEL-NEXT: lsl x11, x10, x8
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; GISEL-NEXT: lsr x8, x10, x8
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; GISEL-NEXT: orr x10, x11, x9, lsr #0
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; GISEL-NEXT: tst wzr, #0x1
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; GISEL-NEXT: csel x8, x10, x8, ne
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; GISEL-NEXT: csel x8, x9, x8, ne
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; GISEL-NEXT: lsr x8, x9, x8
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; GISEL-NEXT: ldr w0, [x8, #20]
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; GISEL-NEXT: ret
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