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AVX512: Remove VSHRI kmask patterns from TD file. It is incorrect to use kshiftw to implement VSHRI v4i1 , bits 15-4 is undef so the upper bits of v4i1 may not be zeroed. v4i1 should be zero_extend to v16i1 ( or any natively supported vector).
Differential Revision: http://reviews.llvm.org/D17763 llvm-svn: 262797
This commit is contained in:
Igor Breger
parent
2c4c7d140a
commit
d0d6119cbd
@ -4702,7 +4702,8 @@ static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
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}
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/// Insert i1-subvector to i1-vector.
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static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
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static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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SDLoc dl(Op);
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SDValue Vec = Op.getOperand(0);
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@ -4732,43 +4733,71 @@ static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
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// 3. Subvector should be inserted in the middle (for example v2i1
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// to v16i1, index 2)
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// extend to natively supported kshift
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MVT MinVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
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MVT WideOpVT = OpVT;
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if (OpVT.getSizeInBits() < MinVT.getStoreSizeInBits())
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WideOpVT = MinVT;
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SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
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SDValue Undef = DAG.getUNDEF(OpVT);
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SDValue WideSubVec =
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DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
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if (Vec.isUndef())
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return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
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DAG.getConstant(IdxVal, dl, MVT::i8));
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SDValue Undef = DAG.getUNDEF(WideOpVT);
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SDValue WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
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Undef, SubVec, ZeroIdx);
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// Extract sub-vector if require.
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auto ExtractSubVec = [&](SDValue V) {
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return (WideOpVT == OpVT) ? V : DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
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OpVT, V, ZeroIdx);
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};
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if (Vec.isUndef()) {
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if (IdxVal != 0) {
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SDValue ShiftBits = DAG.getConstant(IdxVal, dl, MVT::i8);
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WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, WideSubVec, ShiftBits);
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}
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return ExtractSubVec(WideSubVec);
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}
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if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
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NumElems = WideOpVT.getVectorNumElements();
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unsigned ShiftLeft = NumElems - SubVecNumElems;
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unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
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WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
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DAG.getConstant(ShiftLeft, dl, MVT::i8));
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return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
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DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
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Vec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, WideSubVec,
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DAG.getConstant(ShiftLeft, dl, MVT::i8));
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Vec = ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, WideOpVT, Vec,
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DAG.getConstant(ShiftRight, dl, MVT::i8)) : Vec;
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return ExtractSubVec(Vec);
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}
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if (IdxVal == 0) {
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// Zero lower bits of the Vec
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SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
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Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
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Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
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// Merge them together
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return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
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Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
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Vec = DAG.getNode(X86ISD::VSRLI, dl, WideOpVT, Vec, ShiftBits);
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Vec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, Vec, ShiftBits);
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// Merge them together, SubVec should be zero extended.
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WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
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getZeroVector(WideOpVT, Subtarget, DAG, dl),
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SubVec, ZeroIdx);
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Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, WideSubVec);
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return ExtractSubVec(Vec);
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}
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// Simple case when we put subvector in the upper part
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if (IdxVal + SubVecNumElems == NumElems) {
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// Zero upper bits of the Vec
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WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
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DAG.getConstant(IdxVal, dl, MVT::i8));
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WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, WideSubVec,
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DAG.getConstant(IdxVal, dl, MVT::i8));
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SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
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Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
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Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
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return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
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Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
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Vec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, Vec, ShiftBits);
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Vec = DAG.getNode(X86ISD::VSRLI, dl, WideOpVT, Vec, ShiftBits);
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Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, WideSubVec);
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return ExtractSubVec(Vec);
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}
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// Subvector should be inserted in the middle - use shuffle
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WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
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SubVec, ZeroIdx);
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SmallVector<int, 64> Mask;
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for (unsigned i = 0; i < NumElems; ++i)
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Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
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@ -12661,7 +12690,7 @@ static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget,
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return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
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if (OpVT.getVectorElementType() == MVT::i1)
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return Insert1BitVector(Op, DAG);
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return Insert1BitVector(Op, DAG, Subtarget);
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return SDValue();
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}
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@ -2445,7 +2445,6 @@ multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
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let Predicates = [HasBWI] in {
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defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
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VEX, TAPD, VEX_W;
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let Predicates = [HasDQI] in
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defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
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VEX, TAPD;
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}
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@ -2482,88 +2481,53 @@ let Predicates = [HasAVX512] in {
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def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
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def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
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}
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def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
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(v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
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def : Pat<(v8i1 (extract_subvector (v32i1 VK32:$src), (iPTR 0))),
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(v8i1 (COPY_TO_REGCLASS VK32:$src, VK8))>;
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def : Pat<(v8i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
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(v8i1 (COPY_TO_REGCLASS VK64:$src, VK8))>;
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// Patterns for kmask insert_subvector/extract_subvector to/from index=0
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multiclass operation_subvector_mask_lowering<RegisterClass subRC, ValueType subVT,
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RegisterClass RC, ValueType VT> {
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def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
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(subVT (COPY_TO_REGCLASS RC:$src, subRC))>;
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def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
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(VT (COPY_TO_REGCLASS subRC:$src, RC))>;
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}
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defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;
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defm : operation_subvector_mask_lowering<VK2, v2i1, VK8, v8i1>;
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defm : operation_subvector_mask_lowering<VK2, v2i1, VK16, v16i1>;
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defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
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defm : operation_subvector_mask_lowering<VK2, v2i1, VK64, v64i1>;
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defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>;
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defm : operation_subvector_mask_lowering<VK4, v4i1, VK16, v16i1>;
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defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
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defm : operation_subvector_mask_lowering<VK4, v4i1, VK64, v64i1>;
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defm : operation_subvector_mask_lowering<VK8, v8i1, VK16, v16i1>;
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defm : operation_subvector_mask_lowering<VK8, v8i1, VK32, v32i1>;
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defm : operation_subvector_mask_lowering<VK8, v8i1, VK64, v64i1>;
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defm : operation_subvector_mask_lowering<VK16, v16i1, VK32, v32i1>;
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defm : operation_subvector_mask_lowering<VK16, v16i1, VK64, v64i1>;
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defm : operation_subvector_mask_lowering<VK32, v32i1, VK64, v64i1>;
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def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
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(v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
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def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 0))),
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(v16i1 (COPY_TO_REGCLASS VK32:$src, VK16))>;
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def : Pat<(v16i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
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(v16i1 (COPY_TO_REGCLASS VK64:$src, VK16))>;
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def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))),
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(v16i1 (COPY_TO_REGCLASS (KSHIFTRDri VK32:$src, (i8 16)), VK16))>;
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def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
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(v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
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def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
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(v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
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def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
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(v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
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def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
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(v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
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def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
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(v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
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def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
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(v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
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def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
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(v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
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def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
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(v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
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def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
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(v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
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def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
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(v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
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def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
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(v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
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def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
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(v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
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def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
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(v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
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def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
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(v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
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def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
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(v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
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def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
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(v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
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def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
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(v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
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def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
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(v8i1 (COPY_TO_REGCLASS
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(KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
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(I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
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def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
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(v8i1 (COPY_TO_REGCLASS
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(KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
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(I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
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def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
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(v4i1 (COPY_TO_REGCLASS
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(KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
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(I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
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def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
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(v4i1 (COPY_TO_REGCLASS
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(KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
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(I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - Aligned and unaligned load and store
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//
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@ -60,9 +60,12 @@ define <8 x i1> @test4(<4 x i1> %a, <4 x i1>%b) {
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; CHECK: # BB#0:
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vptestmd %xmm0, %xmm0, %k0
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; CHECK-NEXT: vpslld $31, %xmm1, %xmm0
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; CHECK-NEXT: vptestmd %xmm0, %xmm0, %k1
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; CHECK-NEXT: kshiftlb $4, %k1, %k1
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; CHECK-NEXT: kshiftlb $4, %k0, %k0
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; CHECK-NEXT: kshiftrb $4, %k0, %k1
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; CHECK-NEXT: korb %k0, %k1, %k0
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; CHECK-NEXT: kshiftrb $4, %k0, %k0
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; CHECK-NEXT: korb %k1, %k0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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@ -75,9 +78,12 @@ define <4 x i1> @test5(<2 x i1> %a, <2 x i1>%b) {
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; CHECK: # BB#0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vptestmq %xmm0, %xmm0, %k0
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; CHECK-NEXT: kshiftlw $2, %k0, %k0
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; CHECK-NEXT: kshiftrw $2, %k0, %k1
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; CHECK-NEXT: korw %k0, %k1, %k0
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; CHECK-NEXT: vpsllq $63, %xmm1, %xmm0
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; CHECK-NEXT: vptestmq %xmm0, %xmm0, %k1
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; CHECK-NEXT: kshiftlb $2, %k1, %k1
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; CHECK-NEXT: kshiftlb $2, %k0, %k0
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; CHECK-NEXT: kshiftrb $2, %k0, %k0
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; CHECK-NEXT: korb %k1, %k0, %k0
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; CHECK-NEXT: vpmovm2d %k0, %xmm0
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; CHECK-NEXT: retq
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@ -90,9 +96,12 @@ define <16 x i1> @test6(<2 x i1> %a, <2 x i1>%b) {
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; CHECK: # BB#0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vptestmq %xmm0, %xmm0, %k0
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; CHECK-NEXT: kshiftlw $2, %k0, %k0
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; CHECK-NEXT: kshiftrw $2, %k0, %k1
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; CHECK-NEXT: korw %k0, %k1, %k0
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; CHECK-NEXT: vpsllq $63, %xmm1, %xmm0
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; CHECK-NEXT: vptestmq %xmm0, %xmm0, %k1
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; CHECK-NEXT: kshiftlb $2, %k1, %k1
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; CHECK-NEXT: kshiftlb $2, %k0, %k0
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; CHECK-NEXT: kshiftrb $2, %k0, %k0
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; CHECK-NEXT: korb %k1, %k0, %k0
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; CHECK-NEXT: kunpckbw %k0, %k0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %xmm0
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; CHECK-NEXT: retq
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@ -106,9 +115,12 @@ define <32 x i1> @test7(<4 x i1> %a, <4 x i1>%b) {
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; CHECK: # BB#0:
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vptestmd %xmm0, %xmm0, %k0
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; CHECK-NEXT: vpslld $31, %xmm1, %xmm0
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; CHECK-NEXT: vptestmd %xmm0, %xmm0, %k1
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; CHECK-NEXT: kshiftlb $4, %k1, %k1
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; CHECK-NEXT: kshiftlb $4, %k0, %k0
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; CHECK-NEXT: kshiftrb $4, %k0, %k1
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; CHECK-NEXT: korb %k0, %k1, %k0
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; CHECK-NEXT: kshiftrb $4, %k0, %k0
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; CHECK-NEXT: korb %k1, %k0, %k0
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; CHECK-NEXT: kunpckbw %k0, %k0, %k0
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; CHECK-NEXT: kunpckwd %k0, %k0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %ymm0
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|
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@ -939,8 +939,8 @@ define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) {
|
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; SKX: # BB#0:
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; SKX-NEXT: vpsllq $63, %xmm2, %xmm2
|
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; SKX-NEXT: vptestmq %xmm2, %xmm2, %k0
|
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; SKX-NEXT: kshiftlw $2, %k0, %k0
|
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; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlb $6, %k0, %k0
|
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; SKX-NEXT: kshiftrb $6, %k0, %k1
|
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; SKX-NEXT: vscatterqps %xmm0, (,%ymm1) {%k1}
|
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; SKX-NEXT: retq
|
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;
|
||||
@ -949,8 +949,8 @@ define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) {
|
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; SKX_32-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SKX_32-NEXT: vpsllq $63, %xmm2, %xmm2
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; SKX_32-NEXT: vptestmq %xmm2, %xmm2, %k0
|
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; SKX_32-NEXT: kshiftlw $2, %k0, %k0
|
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; SKX_32-NEXT: kshiftrw $2, %k0, %k1
|
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; SKX_32-NEXT: kshiftlb $6, %k0, %k0
|
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; SKX_32-NEXT: kshiftrb $6, %k0, %k1
|
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; SKX_32-NEXT: vscatterdps %xmm0, (,%xmm1) {%k1}
|
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; SKX_32-NEXT: retl
|
||||
call void @llvm.masked.scatter.v2f32(<2 x float> %a1, <2 x float*> %ptr, i32 4, <2 x i1> %mask)
|
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@ -984,8 +984,8 @@ define void @test21(<2 x i32>%a1, <2 x i32*> %ptr, <2 x i1>%mask) {
|
||||
; SKX: # BB#0:
|
||||
; SKX-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; SKX-NEXT: vptestmq %xmm2, %xmm2, %k0
|
||||
; SKX-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlb $6, %k0, %k0
|
||||
; SKX-NEXT: kshiftrb $6, %k0, %k1
|
||||
; SKX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; SKX-NEXT: vpscatterqd %xmm0, (,%ymm1) {%k1}
|
||||
; SKX-NEXT: retq
|
||||
@ -994,8 +994,8 @@ define void @test21(<2 x i32>%a1, <2 x i32*> %ptr, <2 x i1>%mask) {
|
||||
; SKX_32: # BB#0:
|
||||
; SKX_32-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; SKX_32-NEXT: vptestmq %xmm2, %xmm2, %k0
|
||||
; SKX_32-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX_32-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX_32-NEXT: kshiftlb $6, %k0, %k0
|
||||
; SKX_32-NEXT: kshiftrb $6, %k0, %k1
|
||||
; SKX_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; SKX_32-NEXT: vpscatterqd %xmm0, (,%ymm1) {%k1}
|
||||
; SKX_32-NEXT: retl
|
||||
@ -1043,8 +1043,8 @@ define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x fl
|
||||
; SKX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; SKX-NEXT: vpsllq $63, %xmm1, %xmm1
|
||||
; SKX-NEXT: vptestmq %xmm1, %xmm1, %k0
|
||||
; SKX-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlb $6, %k0, %k0
|
||||
; SKX-NEXT: kshiftrb $6, %k0, %k1
|
||||
; SKX-NEXT: vgatherdps (%rdi,%xmm0,4), %xmm2 {%k1}
|
||||
; SKX-NEXT: vmovaps %zmm2, %zmm0
|
||||
; SKX-NEXT: retq
|
||||
@ -1054,8 +1054,8 @@ define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x fl
|
||||
; SKX_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; SKX_32-NEXT: vpsllq $63, %xmm1, %xmm1
|
||||
; SKX_32-NEXT: vptestmq %xmm1, %xmm1, %k0
|
||||
; SKX_32-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX_32-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX_32-NEXT: kshiftlb $6, %k0, %k0
|
||||
; SKX_32-NEXT: kshiftrb $6, %k0, %k1
|
||||
; SKX_32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; SKX_32-NEXT: vgatherdps (%eax,%xmm0,4), %xmm2 {%k1}
|
||||
; SKX_32-NEXT: vmovaps %zmm2, %zmm0
|
||||
|
||||
@ -707,8 +707,8 @@ define void @test14(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
|
||||
; SKX-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; SKX-NEXT: vpcmpeqq %xmm2, %xmm0, %k0
|
||||
; SKX-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlw $14, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $14, %k0, %k1
|
||||
; SKX-NEXT: vmovups %xmm1, (%rdi) {%k1}
|
||||
; SKX-NEXT: retq
|
||||
%mask = icmp eq <2 x i32> %trigger, zeroinitializer
|
||||
@ -801,8 +801,8 @@ define <2 x float> @test16(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %
|
||||
; SKX-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; SKX-NEXT: vpcmpeqq %xmm2, %xmm0, %k0
|
||||
; SKX-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlw $14, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $14, %k0, %k1
|
||||
; SKX-NEXT: vmovups (%rdi), %xmm1 {%k1}
|
||||
; SKX-NEXT: vmovaps %zmm1, %zmm0
|
||||
; SKX-NEXT: retq
|
||||
@ -856,8 +856,8 @@ define <2 x i32> @test17(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) {
|
||||
; SKX-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; SKX-NEXT: vpcmpeqq %xmm2, %xmm0, %k0
|
||||
; SKX-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlw $14, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $14, %k0, %k1
|
||||
; SKX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
|
||||
; SKX-NEXT: vmovdqu32 (%rdi), %xmm0 {%k1}
|
||||
; SKX-NEXT: vpmovsxdq %xmm0, %xmm0
|
||||
@ -903,8 +903,8 @@ define <2 x float> @test18(<2 x i32> %trigger, <2 x float>* %addr) {
|
||||
; SKX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; SKX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0
|
||||
; SKX-NEXT: kshiftlw $2, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $2, %k0, %k1
|
||||
; SKX-NEXT: kshiftlw $14, %k0, %k0
|
||||
; SKX-NEXT: kshiftrw $14, %k0, %k1
|
||||
; SKX-NEXT: vmovups (%rdi), %xmm0 {%k1} {z}
|
||||
; SKX-NEXT: retq
|
||||
%mask = icmp eq <2 x i32> %trigger, zeroinitializer
|
||||
|
||||
Loading…
Reference in New Issue
Block a user