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llvm-svn: 195237
This commit is contained in:
NAKAMURA Takumi
parent
6373ea3e86
commit
d114df4bce
@ -4208,7 +4208,7 @@ static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
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unsigned NumLanes = VT.getSizeInBits()/128;
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unsigned LaneSize = NumElts/NumLanes;
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// 2 or 4 elements in one lane
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SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
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for (unsigned l = 0; l != NumElts; l += LaneSize) {
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for (unsigned i = 0; i != LaneSize; ++i) {
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@ -7663,7 +7663,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
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MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
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MaskEltVT.getSizeInBits());
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Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
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SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
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getZeroVector(MaskVT, Subtarget, DAG, dl),
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@ -8988,7 +8988,7 @@ static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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MVT VT = Op.getSimpleValueType();
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MVT VT = Op.getSimpleValueType();
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SDValue In = Op.getOperand(0);
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MVT InVT = In.getSimpleValueType();
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assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
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@ -9947,7 +9947,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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// operations may be required for some comparisons.
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unsigned Opc;
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bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
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switch (SetCCOpcode) {
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default: llvm_unreachable("Unexpected SETCC condition");
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case ISD::SETNE: Invert = true;
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@ -9964,23 +9964,23 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
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FlipSigns = true; Invert = true; break;
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}
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// Special case: Use min/max operations for SETULE/SETUGE
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MVT VET = VT.getVectorElementType();
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bool hasMinMax =
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(Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
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|| (Subtarget->hasSSE2() && (VET == MVT::i8));
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if (hasMinMax) {
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
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case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
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}
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if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
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}
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if (Swap)
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std::swap(Op0, Op1);
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@ -10067,7 +10067,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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// If the logical-not of the result is required, perform that now.
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if (Invert)
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Result = DAG.getNOT(dl, Result, VT);
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if (MinMax)
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Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
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@ -11231,7 +11231,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_sse41_pminsd:
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case Intrinsic::x86_avx2_pmins_b:
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case Intrinsic::x86_avx2_pmins_w:
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case Intrinsic::x86_avx2_pmins_d:
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case Intrinsic::x86_avx2_pmins_d:
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case Intrinsic::x86_avx512_pmins_d:
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case Intrinsic::x86_avx512_pmins_q: {
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unsigned Opcode;
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@ -11673,7 +11673,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_fma_vfmaddsub_ps_512:
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case Intrinsic::x86_fma_vfmaddsub_pd_512:
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case Intrinsic::x86_fma_vfmsubadd_ps_512:
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case Intrinsic::x86_fma_vfmsubadd_pd_512: {
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case Intrinsic::x86_fma_vfmsubadd_pd_512: {
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unsigned Opc;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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@ -11741,8 +11741,8 @@ static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
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assert(C && "Invalid scale type");
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SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
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SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
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EVT MaskVT = MVT::getVectorVT(MVT::i1,
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SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
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EVT MaskVT = MVT::getVectorVT(MVT::i1,
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Index.getValueType().getVectorNumElements());
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SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
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@ -11769,7 +11769,7 @@ static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
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SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
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SDValue Segment = DAG.getRegister(0, MVT::i32);
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if (Src.getOpcode() == ISD::UNDEF)
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Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
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Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
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SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
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SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
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SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
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@ -11887,7 +11887,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
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unsigned Opc;
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switch (IntNo) {
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::x86_avx512_gather_qps_mask_512:
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case Intrinsic::x86_avx512_gather_qps_mask_512:
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Opc = X86::VGATHERQPSZrm; break;
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case Intrinsic::x86_avx512_gather_qpd_mask_512:
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Opc = X86::VGATHERQPDZrm; break;
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@ -11925,7 +11925,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
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unsigned Opc;
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switch (IntNo) {
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::x86_avx512_scatter_qpd_512:
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case Intrinsic::x86_avx512_scatter_qpd_512:
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Opc = X86::VSCATTERQPDZmr; break;
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case Intrinsic::x86_avx512_scatter_qps_512:
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Opc = X86::VSCATTERQPSZmr; break;
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@ -11961,7 +11961,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
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unsigned Opc;
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switch (IntNo) {
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::x86_avx512_scatter_qpd_mask_512:
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case Intrinsic::x86_avx512_scatter_qpd_mask_512:
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Opc = X86::VSCATTERQPDZmr; break;
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case Intrinsic::x86_avx512_scatter_qps_mask_512:
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Opc = X86::VSCATTERQPSZmr; break;
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@ -12602,7 +12602,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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// Make a large shift.
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SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
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MVT::v8i16, R, ShiftAmt,
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DAG);
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DAG);
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SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
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// Zero out the rightmost bits.
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SmallVector<SDValue, 16> V(16,
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@ -16375,7 +16375,7 @@ static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
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MVT VecVT = Vec.getSimpleValueType();
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SDValue Idx = N->getOperand(1);
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MVT EltVT = N->getSimpleValueType(0);
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assert((VecVT.getVectorElementType() == MVT::i1 && EltVT == MVT::i8) ||
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"Unexpected operands in ExtractBitFromMaskVector");
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@ -16393,7 +16393,7 @@ static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
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MVT ScalarVT = MVT::getIntegerVT(VecVT.getSizeInBits());
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unsigned MaxShift = VecVT.getSizeInBits() - 1;
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Vec = DAG.getNode(ISD::BITCAST, dl, ScalarVT, Vec);
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Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec,
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Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec,
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DAG.getConstant(MaxShift - IdxVal, ScalarVT));
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Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec,
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DAG.getConstant(MaxShift, ScalarVT));
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@ -17447,7 +17447,7 @@ static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
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}
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/// \brief Returns a vector of 0s if the node in input is a vector logical
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/// shift by a constant amount which is known to be bigger than or equal
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/// shift by a constant amount which is known to be bigger than or equal
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/// to the vector element size in bits.
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static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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@ -17467,7 +17467,7 @@ static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
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unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
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// SSE2/AVX2 logical shifts always return a vector of 0s
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// if the shift amount is bigger than or equal to
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// if the shift amount is bigger than or equal to
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// the element size. The constant shift amount will be
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// encoded as a 8-bit immediate.
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if (ShiftAmt.trunc(8).uge(MaxAmount))
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