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llvm-svn: 195237
This commit is contained in:
NAKAMURA Takumi 2013-11-20 10:55:15 +00:00
parent 6373ea3e86
commit d114df4bce
1 changed files with 22 additions and 22 deletions
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44
lib/Target/X86/X86ISelLowering.cpp
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@ -4208,7 +4208,7 @@ static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
unsigned NumLanes = VT.getSizeInBits()/128; unsigned NumLanes = VT.getSizeInBits()/128;
unsigned LaneSize = NumElts/NumLanes; unsigned LaneSize = NumElts/NumLanes;
// 2 or 4 elements in one lane // 2 or 4 elements in one lane
SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1); SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
for (unsigned l = 0; l != NumElts; l += LaneSize) { for (unsigned l = 0; l != NumElts; l += LaneSize) {
for (unsigned i = 0; i != LaneSize; ++i) { for (unsigned i = 0; i != LaneSize; ++i) {
@ -7663,7 +7663,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits()); MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() / MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
MaskEltVT.getSizeInBits()); MaskEltVT.getSizeInBits());
Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT); Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT, SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
getZeroVector(MaskVT, Subtarget, DAG, dl), getZeroVector(MaskVT, Subtarget, DAG, dl),
@ -8988,7 +8988,7 @@ static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
SDValue In = Op.getOperand(0); SDValue In = Op.getOperand(0);
MVT InVT = In.getSimpleValueType(); MVT InVT = In.getSimpleValueType();
assert(VT.getVectorNumElements() == InVT.getVectorNumElements() && assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
@ -9947,7 +9947,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
// operations may be required for some comparisons. // operations may be required for some comparisons.
unsigned Opc; unsigned Opc;
bool Swap = false, Invert = false, FlipSigns = false, MinMax = false; bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
switch (SetCCOpcode) { switch (SetCCOpcode) {
default: llvm_unreachable("Unexpected SETCC condition"); default: llvm_unreachable("Unexpected SETCC condition");
case ISD::SETNE: Invert = true; case ISD::SETNE: Invert = true;
@ -9964,23 +9964,23 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
FlipSigns = true; Invert = true; break; FlipSigns = true; Invert = true; break;
} }
// Special case: Use min/max operations for SETULE/SETUGE // Special case: Use min/max operations for SETULE/SETUGE
MVT VET = VT.getVectorElementType(); MVT VET = VT.getVectorElementType();
bool hasMinMax = bool hasMinMax =
(Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32)) (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
|| (Subtarget->hasSSE2() && (VET == MVT::i8)); || (Subtarget->hasSSE2() && (VET == MVT::i8));
if (hasMinMax) { if (hasMinMax) {
switch (SetCCOpcode) { switch (SetCCOpcode) {
default: break; default: break;
case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break; case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break; case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
} }
if (MinMax) { Swap = false; Invert = false; FlipSigns = false; } if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
} }
if (Swap) if (Swap)
std::swap(Op0, Op1); std::swap(Op0, Op1);
@ -10067,7 +10067,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
// If the logical-not of the result is required, perform that now. // If the logical-not of the result is required, perform that now.
if (Invert) if (Invert)
Result = DAG.getNOT(dl, Result, VT); Result = DAG.getNOT(dl, Result, VT);
if (MinMax) if (MinMax)
Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result); Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
@ -11231,7 +11231,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
case Intrinsic::x86_sse41_pminsd: case Intrinsic::x86_sse41_pminsd:
case Intrinsic::x86_avx2_pmins_b: case Intrinsic::x86_avx2_pmins_b:
case Intrinsic::x86_avx2_pmins_w: case Intrinsic::x86_avx2_pmins_w:
case Intrinsic::x86_avx2_pmins_d: case Intrinsic::x86_avx2_pmins_d:
case Intrinsic::x86_avx512_pmins_d: case Intrinsic::x86_avx512_pmins_d:
case Intrinsic::x86_avx512_pmins_q: { case Intrinsic::x86_avx512_pmins_q: {
unsigned Opcode; unsigned Opcode;
@ -11673,7 +11673,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
case Intrinsic::x86_fma_vfmaddsub_ps_512: case Intrinsic::x86_fma_vfmaddsub_ps_512:
case Intrinsic::x86_fma_vfmaddsub_pd_512: case Intrinsic::x86_fma_vfmaddsub_pd_512:
case Intrinsic::x86_fma_vfmsubadd_ps_512: case Intrinsic::x86_fma_vfmsubadd_ps_512:
case Intrinsic::x86_fma_vfmsubadd_pd_512: { case Intrinsic::x86_fma_vfmsubadd_pd_512: {
unsigned Opc; unsigned Opc;
switch (IntNo) { switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
@ -11741,8 +11741,8 @@ static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp); ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
assert(C && "Invalid scale type"); assert(C && "Invalid scale type");
SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8); SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl); SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
EVT MaskVT = MVT::getVectorVT(MVT::i1, EVT MaskVT = MVT::getVectorVT(MVT::i1,
Index.getValueType().getVectorNumElements()); Index.getValueType().getVectorNumElements());
SDValue MaskInReg = DAG.getConstant(~0, MaskVT); SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other); SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
@ -11769,7 +11769,7 @@ static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
SDValue Disp = DAG.getTargetConstant(0, MVT::i32); SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
SDValue Segment = DAG.getRegister(0, MVT::i32); SDValue Segment = DAG.getRegister(0, MVT::i32);
if (Src.getOpcode() == ISD::UNDEF) if (Src.getOpcode() == ISD::UNDEF)
Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl); Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain}; SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops); SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) }; SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
@ -11887,7 +11887,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
unsigned Opc; unsigned Opc;
switch (IntNo) { switch (IntNo) {
default: llvm_unreachable("Unexpected intrinsic!"); default: llvm_unreachable("Unexpected intrinsic!");
case Intrinsic::x86_avx512_gather_qps_mask_512: case Intrinsic::x86_avx512_gather_qps_mask_512:
Opc = X86::VGATHERQPSZrm; break; Opc = X86::VGATHERQPSZrm; break;
case Intrinsic::x86_avx512_gather_qpd_mask_512: case Intrinsic::x86_avx512_gather_qpd_mask_512:
Opc = X86::VGATHERQPDZrm; break; Opc = X86::VGATHERQPDZrm; break;
@ -11925,7 +11925,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
unsigned Opc; unsigned Opc;
switch (IntNo) { switch (IntNo) {
default: llvm_unreachable("Unexpected intrinsic!"); default: llvm_unreachable("Unexpected intrinsic!");
case Intrinsic::x86_avx512_scatter_qpd_512: case Intrinsic::x86_avx512_scatter_qpd_512:
Opc = X86::VSCATTERQPDZmr; break; Opc = X86::VSCATTERQPDZmr; break;
case Intrinsic::x86_avx512_scatter_qps_512: case Intrinsic::x86_avx512_scatter_qps_512:
Opc = X86::VSCATTERQPSZmr; break; Opc = X86::VSCATTERQPSZmr; break;
@ -11961,7 +11961,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
unsigned Opc; unsigned Opc;
switch (IntNo) { switch (IntNo) {
default: llvm_unreachable("Unexpected intrinsic!"); default: llvm_unreachable("Unexpected intrinsic!");
case Intrinsic::x86_avx512_scatter_qpd_mask_512: case Intrinsic::x86_avx512_scatter_qpd_mask_512:
Opc = X86::VSCATTERQPDZmr; break; Opc = X86::VSCATTERQPDZmr; break;
case Intrinsic::x86_avx512_scatter_qps_mask_512: case Intrinsic::x86_avx512_scatter_qps_mask_512:
Opc = X86::VSCATTERQPSZmr; break; Opc = X86::VSCATTERQPSZmr; break;
@ -12602,7 +12602,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
// Make a large shift. // Make a large shift.
SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
MVT::v8i16, R, ShiftAmt, MVT::v8i16, R, ShiftAmt,
DAG); DAG);
SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
// Zero out the rightmost bits. // Zero out the rightmost bits.
SmallVector<SDValue, 16> V(16, SmallVector<SDValue, 16> V(16,
@ -16375,7 +16375,7 @@ static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
MVT VecVT = Vec.getSimpleValueType(); MVT VecVT = Vec.getSimpleValueType();
SDValue Idx = N->getOperand(1); SDValue Idx = N->getOperand(1);
MVT EltVT = N->getSimpleValueType(0); MVT EltVT = N->getSimpleValueType(0);
assert((VecVT.getVectorElementType() == MVT::i1 && EltVT == MVT::i8) || assert((VecVT.getVectorElementType() == MVT::i1 && EltVT == MVT::i8) ||
"Unexpected operands in ExtractBitFromMaskVector"); "Unexpected operands in ExtractBitFromMaskVector");
@ -16393,7 +16393,7 @@ static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
MVT ScalarVT = MVT::getIntegerVT(VecVT.getSizeInBits()); MVT ScalarVT = MVT::getIntegerVT(VecVT.getSizeInBits());
unsigned MaxShift = VecVT.getSizeInBits() - 1; unsigned MaxShift = VecVT.getSizeInBits() - 1;
Vec = DAG.getNode(ISD::BITCAST, dl, ScalarVT, Vec); Vec = DAG.getNode(ISD::BITCAST, dl, ScalarVT, Vec);
Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec, Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec,
DAG.getConstant(MaxShift - IdxVal, ScalarVT)); DAG.getConstant(MaxShift - IdxVal, ScalarVT));
Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec, Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec,
DAG.getConstant(MaxShift, ScalarVT)); DAG.getConstant(MaxShift, ScalarVT));
@ -17447,7 +17447,7 @@ static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
} }
/// \brief Returns a vector of 0s if the node in input is a vector logical /// \brief Returns a vector of 0s if the node in input is a vector logical
/// shift by a constant amount which is known to be bigger than or equal /// shift by a constant amount which is known to be bigger than or equal
/// to the vector element size in bits. /// to the vector element size in bits.
static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG, static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
@ -17467,7 +17467,7 @@ static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
unsigned MaxAmount = VT.getVectorElementType().getSizeInBits(); unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
// SSE2/AVX2 logical shifts always return a vector of 0s // SSE2/AVX2 logical shifts always return a vector of 0s
// if the shift amount is bigger than or equal to // if the shift amount is bigger than or equal to
// the element size. The constant shift amount will be // the element size. The constant shift amount will be
// encoded as a 8-bit immediate. // encoded as a 8-bit immediate.
if (ShiftAmt.trunc(8).uge(MaxAmount)) if (ShiftAmt.trunc(8).uge(MaxAmount))