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[PPC64] Add vector pack/unpack support from ISA 2.07
This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. Appropriate tests have been added. There is a companion patch to clang for the rest of this support. llvm-svn: 237499
This commit is contained in:
Bill Schmidt
parent
1882033972
commit
d115a77d30
@ -480,6 +480,12 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
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def int_ppc_altivec_vpkswus : GCCBuiltin<"__builtin_altivec_vpkswus">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vpksdss : GCCBuiltin<"__builtin_altivec_vpksdss">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vpksdus : GCCBuiltin<"__builtin_altivec_vpksdus">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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// vpkuhum is lowered to a shuffle.
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def int_ppc_altivec_vpkuhus : GCCBuiltin<"__builtin_altivec_vpkuhus">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
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@ -488,6 +494,10 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
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def int_ppc_altivec_vpkuwus : GCCBuiltin<"__builtin_altivec_vpkuwus">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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// vpkudum is lowered to a shuffle.
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def int_ppc_altivec_vpkudus : GCCBuiltin<"__builtin_altivec_vpkudus">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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// Unpacks.
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def int_ppc_altivec_vupkhpx : GCCBuiltin<"__builtin_altivec_vupkhpx">,
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@ -496,12 +506,16 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_altivec_vupkhsh : GCCBuiltin<"__builtin_altivec_vupkhsh">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
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def int_ppc_altivec_vupkhsw : GCCBuiltin<"__builtin_altivec_vupkhsw">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
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def int_ppc_altivec_vupklpx : GCCBuiltin<"__builtin_altivec_vupklpx">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
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def int_ppc_altivec_vupklsb : GCCBuiltin<"__builtin_altivec_vupklsb">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_altivec_vupklsh : GCCBuiltin<"__builtin_altivec_vupklsh">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
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def int_ppc_altivec_vupklsw : GCCBuiltin<"__builtin_altivec_vupklsw">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
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// FP <-> integer conversion.
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@ -1101,7 +1101,7 @@ static bool isConstantOrUndef(int Op, int Val) {
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/// VPKUHUM instruction.
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/// The ShuffleKind distinguishes between big-endian operations with
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/// two different inputs (0), either-endian operations with two identical
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/// inputs (1), and little-endian operantion with two different inputs (2).
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/// inputs (1), and little-endian operations with two different inputs (2).
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/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
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bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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SelectionDAG &DAG) {
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@ -1132,7 +1132,7 @@ bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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/// VPKUWUM instruction.
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/// The ShuffleKind distinguishes between big-endian operations with
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/// two different inputs (0), either-endian operations with two identical
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/// inputs (1), and little-endian operantion with two different inputs (2).
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/// inputs (1), and little-endian operations with two different inputs (2).
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/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
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bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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SelectionDAG &DAG) {
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@ -1163,6 +1163,49 @@ bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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return true;
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}
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/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUDUM instruction.
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/// The ShuffleKind distinguishes between big-endian operations with
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/// two different inputs (0), either-endian operations with two identical
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/// inputs (1), and little-endian operations with two different inputs (2).
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/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
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bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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SelectionDAG &DAG) {
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bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
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if (ShuffleKind == 0) {
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if (IsLE)
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return false;
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for (unsigned i = 0; i != 16; i += 4)
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if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
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!isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
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!isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
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!isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
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return false;
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} else if (ShuffleKind == 2) {
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if (!IsLE)
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return false;
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for (unsigned i = 0; i != 16; i += 4)
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if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
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!isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
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!isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
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!isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
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return false;
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} else if (ShuffleKind == 1) {
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unsigned j = IsLE ? 0 : 4;
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for (unsigned i = 0; i != 8; i += 4)
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if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
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!isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
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!isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
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!isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
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!isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
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!isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
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!isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
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!isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
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return false;
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}
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return true;
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}
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/// isVMerge - Common function, used to match vmrg* shuffles.
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///
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static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
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@ -6993,6 +7036,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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PPC::isSplatShuffleMask(SVOp, 4) ||
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PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
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PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
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PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
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PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
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PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
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@ -7010,6 +7054,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
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if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
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PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
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PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
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PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
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PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
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@ -357,6 +357,11 @@ namespace llvm {
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bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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SelectionDAG &DAG);
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/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUDUM instruction.
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bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
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SelectionDAG &DAG);
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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@ -43,6 +43,10 @@ def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
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}]>;
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def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
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}]>;
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def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
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@ -51,6 +55,10 @@ def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
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}]>;
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def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
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}]>;
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// These fragments are provided for little-endian, where the inputs must be
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// swapped for correct semantics.
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@ -62,6 +70,10 @@ def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
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}]>;
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def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
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}]>;
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def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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@ -1091,6 +1103,29 @@ def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
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def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
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int_ppc_altivec_crypto_vpermxor, v16i8>;
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// Vector doubleword integer pack and unpack.
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def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,
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v4i32, v2i64>;
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def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,
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v4i32, v2i64>;
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def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vpkudum $vD, $vA, $vB", IIC_VecFP,
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[(set v16i8:$vD,
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(vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>;
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def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,
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v4i32, v2i64>;
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def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw,
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v2i64, v4i32>;
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def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
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v2i64, v4i32>;
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// Shuffle patterns for unary and swapped (LE) vector pack modulo.
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def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef),
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(VPKUDUM $vA, $vA)>;
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def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB),
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(VPKUDUM $vB, $vA)>;
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} // end HasP8Altivec
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// Crypto instructions (from builtins)
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@ -382,8 +382,12 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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case PPC::VPKPX:
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case PPC::VPKSHSS:
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case PPC::VPKSHUS:
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case PPC::VPKSDSS:
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case PPC::VPKSDUS:
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case PPC::VPKSWSS:
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case PPC::VPKSWUS:
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case PPC::VPKUDUM:
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case PPC::VPKUDUS:
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case PPC::VPKUHUM:
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case PPC::VPKUHUS:
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case PPC::VPKUWUM:
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@ -412,9 +416,11 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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case PPC::VUPKHPX:
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case PPC::VUPKHSB:
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case PPC::VUPKHSH:
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case PPC::VUPKHSW:
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case PPC::VUPKLPX:
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case PPC::VUPKLSB:
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case PPC::VUPKLSH:
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case PPC::VUPKLSW:
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case PPC::XXMRGHW:
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case PPC::XXMRGLW:
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case PPC::XXSPLTW:
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43
test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
Normal file
43
test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
Normal file
@ -0,0 +1,43 @@
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
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define void @VPKUDUM_unary(<2 x i64>* %A) {
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entry:
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%tmp = load <2 x i64>, <2 x i64>* %A
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%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
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%tmp3 = extractelement <4 x i32> %tmp2, i32 1
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%tmp4 = extractelement <4 x i32> %tmp2, i32 3
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%tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0
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%tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1
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%tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2
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%tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3
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%tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64>
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store <2 x i64> %tmp9, <2 x i64>* %A
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ret void
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}
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; CHECK-LABEL: @VPKUDUM_unary
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; CHECK-NOT: vperm
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; CHECK: vpkudum
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define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
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entry:
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%tmp = load <2 x i64>, <2 x i64>* %A
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%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
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%tmp3 = load <2 x i64>, <2 x i64>* %B
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%tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32>
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%tmp5 = extractelement <4 x i32> %tmp2, i32 1
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%tmp6 = extractelement <4 x i32> %tmp2, i32 3
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%tmp7 = extractelement <4 x i32> %tmp4, i32 1
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%tmp8 = extractelement <4 x i32> %tmp4, i32 3
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%tmp9 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
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%tmp10 = insertelement <4 x i32> %tmp9, i32 %tmp6, i32 1
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%tmp11 = insertelement <4 x i32> %tmp10, i32 %tmp7, i32 2
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%tmp12 = insertelement <4 x i32> %tmp11, i32 %tmp8, i32 3
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%tmp13 = bitcast <4 x i32> %tmp12 to <2 x i64>
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store <2 x i64> %tmp13, <2 x i64>* %A
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ret void
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}
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; CHECK-LABEL: @VPKUDUM
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; CHECK-NOT: vperm
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; CHECK: vpkudum
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43
test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
Normal file
43
test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
Normal file
@ -0,0 +1,43 @@
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
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define void @VPKUDUM_unary(<2 x i64>* %A) {
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entry:
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%tmp = load <2 x i64>, <2 x i64>* %A
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%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
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%tmp3 = extractelement <4 x i32> %tmp2, i32 0
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%tmp4 = extractelement <4 x i32> %tmp2, i32 2
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%tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0
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%tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1
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%tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2
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%tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3
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%tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64>
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store <2 x i64> %tmp9, <2 x i64>* %A
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ret void
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}
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; CHECK-LABEL: @VPKUDUM_unary
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; CHECK-NOT: vperm
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; CHECK: vpkudum
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define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
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entry:
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%tmp = load <2 x i64>, <2 x i64>* %A
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||||
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
|
||||
%tmp3 = load <2 x i64>, <2 x i64>* %B
|
||||
%tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32>
|
||||
%tmp5 = extractelement <4 x i32> %tmp2, i32 0
|
||||
%tmp6 = extractelement <4 x i32> %tmp2, i32 2
|
||||
%tmp7 = extractelement <4 x i32> %tmp4, i32 0
|
||||
%tmp8 = extractelement <4 x i32> %tmp4, i32 2
|
||||
%tmp9 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
|
||||
%tmp10 = insertelement <4 x i32> %tmp9, i32 %tmp6, i32 1
|
||||
%tmp11 = insertelement <4 x i32> %tmp10, i32 %tmp7, i32 2
|
||||
%tmp12 = insertelement <4 x i32> %tmp11, i32 %tmp8, i32 3
|
||||
%tmp13 = bitcast <4 x i32> %tmp12 to <2 x i64>
|
||||
store <2 x i64> %tmp13, <2 x i64>* %A
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @VPKUDUM
|
||||
; CHECK-NOT: vperm
|
||||
; CHECK: vpkudum
|
||||
19
test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt
Normal file
19
test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt
Normal file
@ -0,0 +1,19 @@
|
||||
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr8 | FileCheck %s
|
||||
|
||||
# CHECK: vpksdss 2, 3, 4
|
||||
0x10 0x43 0x25 0xce
|
||||
|
||||
# CHECK: vpksdus 2, 3, 4
|
||||
0x10 0x43 0x25 0x4e
|
||||
|
||||
# CHECK: vpkudus 2, 3, 4
|
||||
0x10 0x43 0x24 0xce
|
||||
|
||||
# CHECK: vpkudum 2, 3, 4
|
||||
0x10 0x43 0x24 0x4e
|
||||
|
||||
# CHECK: vupkhsw 2, 3
|
||||
0x10 0x40 0x1e 0x4e
|
||||
|
||||
# CHECK: vupklsw 2, 3
|
||||
0x10 0x40 0x1e 0xce
|
||||
26
test/MC/PowerPC/ppc64-encoding-p8vector.s
Normal file
26
test/MC/PowerPC/ppc64-encoding-p8vector.s
Normal file
@ -0,0 +1,26 @@
|
||||
# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
|
||||
# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
|
||||
|
||||
# CHECK-BE: vpksdss 2, 3, 4 # encoding: [0x10,0x43,0x25,0xce]
|
||||
# CHECK-LE: vpksdss 2, 3, 4 # encoding: [0xce,0x25,0x43,0x10]
|
||||
vpksdss 2, 3, 4
|
||||
|
||||
# CHECK-BE: vpksdus 2, 3, 4 # encoding: [0x10,0x43,0x25,0x4e]
|
||||
# CHECK-LE: vpksdus 2, 3, 4 # encoding: [0x4e,0x25,0x43,0x10]
|
||||
vpksdus 2, 3, 4
|
||||
|
||||
# CHECK-BE: vpkudus 2, 3, 4 # encoding: [0x10,0x43,0x24,0xce]
|
||||
# CHECK-LE: vpkudus 2, 3, 4 # encoding: [0xce,0x24,0x43,0x10]
|
||||
vpkudus 2, 3, 4
|
||||
|
||||
# CHECK-BE: vpkudum 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4e]
|
||||
# CHECK-LE: vpkudum 2, 3, 4 # encoding: [0x4e,0x24,0x43,0x10]
|
||||
vpkudum 2, 3, 4
|
||||
|
||||
# CHECK-BE: vupkhsw 2, 3 # encoding: [0x10,0x40,0x1e,0x4e]
|
||||
# CHECK-LE: vupkhsw 2, 3 # encoding: [0x4e,0x1e,0x40,0x10]
|
||||
vupkhsw 2, 3
|
||||
|
||||
# CHECK-BE: vupklsw 2, 3 # encoding: [0x10,0x40,0x1e,0xce]
|
||||
# CHECK-LE: vupklsw 2, 3 # encoding: [0xce,0x1e,0x40,0x10]
|
||||
vupklsw 2, 3
|
||||
Loading…
Reference in New Issue
Block a user