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StructurizeCFG: simplify phi nodes when possible
After structurization, some phi nodes can have a single incoming edge and can be simplified away. This change runs a simplify query on all phis that are either modified or added by the structurizer. This also moves some phis closer to their use as a side benefit. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D75500
This commit is contained in:
Sameer Sahasrabuddhe
parent
cac4f78ec3
commit
d13ab42a5a
@ -34,6 +34,7 @@
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#include "llvm/IR/Use.h"
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#include "llvm/IR/User.h"
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#include "llvm/IR/Value.h"
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#include "llvm/IR/ValueHandle.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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@ -197,6 +198,7 @@ class StructurizeCFG : public RegionPass {
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SmallVector<RegionNode *, 8> Order;
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BBSet Visited;
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SmallVector<WeakVH, 8> AffectedPhis;
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BBPhiMap DeletedPhis;
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BB2BBVecMap AddedPhis;
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@ -232,6 +234,8 @@ class StructurizeCFG : public RegionPass {
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void setPhiValues();
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void simplifyAffectedPhis();
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void killTerminator(BasicBlock *BB);
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void changeExit(RegionNode *Node, BasicBlock *NewExit,
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@ -585,9 +589,14 @@ void StructurizeCFG::insertConditions(bool Loops) {
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void StructurizeCFG::delPhiValues(BasicBlock *From, BasicBlock *To) {
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PhiMap &Map = DeletedPhis[To];
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for (PHINode &Phi : To->phis()) {
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bool Recorded = false;
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while (Phi.getBasicBlockIndex(From) != -1) {
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Value *Deleted = Phi.removeIncomingValue(From, false);
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Map[&Phi].push_back(std::make_pair(From, Deleted));
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if (!Recorded) {
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AffectedPhis.push_back(&Phi);
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Recorded = true;
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}
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}
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}
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}
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@ -632,28 +641,29 @@ void StructurizeCFG::setPhiValues() {
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for (BasicBlock *FI : From)
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Phi->setIncomingValueForBlock(FI, Updater.GetValueAtEndOfBlock(FI));
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AffectedPhis.push_back(Phi);
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}
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DeletedPhis.erase(To);
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}
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assert(DeletedPhis.empty());
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// Simplify any phis inserted by the SSAUpdater if possible
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AffectedPhis.append(InsertedPhis.begin(), InsertedPhis.end());
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}
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void StructurizeCFG::simplifyAffectedPhis() {
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bool Changed;
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do {
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Changed = false;
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SimplifyQuery Q(Func->getParent()->getDataLayout());
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Q.DT = DT;
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for (size_t i = 0; i < InsertedPhis.size(); ++i) {
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PHINode *Phi = InsertedPhis[i];
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if (Value *V = SimplifyInstruction(Phi, Q)) {
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Phi->replaceAllUsesWith(V);
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Phi->eraseFromParent();
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InsertedPhis[i] = InsertedPhis.back();
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InsertedPhis.pop_back();
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i--;
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Changed = true;
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for (WeakVH VH : AffectedPhis) {
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if (auto Phi = dyn_cast_or_null<PHINode>(VH)) {
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if (auto NewValue = SimplifyInstruction(Phi, Q)) {
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Phi->replaceAllUsesWith(NewValue);
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Phi->eraseFromParent();
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Changed = true;
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}
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}
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}
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} while (Changed);
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@ -886,6 +896,7 @@ void StructurizeCFG::createFlow() {
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BasicBlock *Exit = ParentRegion->getExit();
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bool EntryDominatesExit = DT->dominates(ParentRegion->getEntry(), Exit);
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AffectedPhis.clear();
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DeletedPhis.clear();
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AddedPhis.clear();
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Conditions.clear();
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@ -1044,6 +1055,7 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassManager &RGM) {
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insertConditions(false);
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insertConditions(true);
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setPhiValues();
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simplifyAffectedPhis();
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rebuildSSA();
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// Cleanup
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@ -91,8 +91,8 @@ define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: bb1:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[MY_TMP2:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
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; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
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; OPT: bb4:
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@ -100,7 +100,6 @@ define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
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; OPT-NEXT: br label [[FLOW]]
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; OPT: Flow:
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; OPT-NEXT: [[MY_TMP2]] = phi i32 [ [[LSR_IV_NEXT]], [[BB4]] ], [ undef, [[BB1]] ]
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; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ undef, [[BB1]] ]
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; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
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@ -185,8 +184,8 @@ define amdgpu_kernel void @constexpr_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: bb1:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[MY_TMP2:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
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; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
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; OPT: bb4:
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@ -194,7 +193,6 @@ define amdgpu_kernel void @constexpr_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
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; OPT-NEXT: br label [[FLOW]]
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; OPT: Flow:
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; OPT-NEXT: [[MY_TMP2]] = phi i32 [ [[LSR_IV_NEXT]], [[BB4]] ], [ undef, [[BB1]] ]
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; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ icmp ne (i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), i32 addrspace(3)* @lds), [[BB1]] ]
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; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
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@ -278,8 +276,8 @@ define amdgpu_kernel void @true_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: bb1:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[MY_TMP2:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
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; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
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; OPT: bb4:
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@ -287,7 +285,6 @@ define amdgpu_kernel void @true_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
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; OPT-NEXT: br label [[FLOW]]
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; OPT: Flow:
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; OPT-NEXT: [[MY_TMP2]] = phi i32 [ [[LSR_IV_NEXT]], [[BB4]] ], [ undef, [[BB1]] ]
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; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ true, [[BB1]] ]
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; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
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@ -367,8 +364,8 @@ define amdgpu_kernel void @false_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: bb1:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[MY_TMP2:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
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; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
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; OPT: bb4:
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@ -376,7 +373,6 @@ define amdgpu_kernel void @false_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
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; OPT-NEXT: br label [[FLOW]]
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; OPT: Flow:
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; OPT-NEXT: [[MY_TMP2]] = phi i32 [ [[LSR_IV_NEXT]], [[BB4]] ], [ undef, [[BB1]] ]
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; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ false, [[BB1]] ]
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; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
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@ -459,8 +455,8 @@ define amdgpu_kernel void @invert_true_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: bb1:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP1:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[MY_TMP2:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
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; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
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; OPT: bb4:
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@ -468,7 +464,6 @@ define amdgpu_kernel void @invert_true_phi_cond_break_loop(i32 %arg) #0 {
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; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
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; OPT-NEXT: br label [[FLOW]]
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; OPT: Flow:
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; OPT-NEXT: [[MY_TMP2]] = phi i32 [ [[LSR_IV_NEXT]], [[BB4]] ], [ undef, [[BB1]] ]
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; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ true, [[BB1]] ]
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; OPT-NEXT: [[TMP0:%.*]] = xor i1 [[MY_TMP3]], true
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; OPT-NEXT: [[TMP1]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP0]], i64 [[PHI_BROKEN]])
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@ -48,8 +48,8 @@ define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* noca
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; IR: bb4:
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; IR-NEXT: br label [[FLOW:%.*]]
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; IR: bb5:
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; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP3:%.*]], [[BB10:%.*]] ], [ 0, [[BB:%.*]] ]
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; IR-NEXT: [[MY_TMP6:%.*]] = phi i32 [ 0, [[BB]] ], [ [[MY_TMP11:%.*]], [[BB10]] ]
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; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP6:%.*]], [[BB10:%.*]] ], [ 0, [[BB:%.*]] ]
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; IR-NEXT: [[MY_TMP6:%.*]] = phi i32 [ 0, [[BB]] ], [ [[TMP5:%.*]], [[BB10]] ]
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; IR-NEXT: [[MY_TMP7:%.*]] = icmp eq i32 [[MY_TMP6]], 1
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; IR-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[MY_TMP7]])
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; IR-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
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@ -60,15 +60,13 @@ define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* noca
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; IR: bb9:
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; IR-NEXT: br i1 false, label [[BB3:%.*]], label [[BB9:%.*]]
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; IR: bb10:
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; IR-NEXT: [[MY_TMP11]] = phi i32 [ [[TMP6:%.*]], [[FLOW]] ]
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; IR-NEXT: [[MY_TMP12:%.*]] = phi i1 [ [[TMP5:%.*]], [[FLOW]] ]
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; IR-NEXT: [[TMP3]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP12]], i64 [[PHI_BROKEN]])
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; IR-NEXT: [[TMP4:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP3]])
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; IR-NEXT: br i1 [[TMP4]], label [[BB23:%.*]], label [[BB5]]
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; IR-NEXT: [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP6]])
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; IR-NEXT: br i1 [[TMP3]], label [[BB23:%.*]], label [[BB5]]
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; IR: Flow:
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; IR-NEXT: [[TMP5]] = phi i1 [ [[MY_TMP22:%.*]], [[BB4]] ], [ true, [[BB5]] ]
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; IR-NEXT: [[TMP6]] = phi i32 [ [[MY_TMP21:%.*]], [[BB4]] ], [ undef, [[BB5]] ]
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; IR-NEXT: [[TMP4:%.*]] = phi i1 [ [[MY_TMP22:%.*]], [[BB4]] ], [ true, [[BB5]] ]
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; IR-NEXT: [[TMP5]] = phi i32 [ [[MY_TMP21:%.*]], [[BB4]] ], [ undef, [[BB5]] ]
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; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
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; IR-NEXT: [[TMP6]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]])
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; IR-NEXT: br label [[BB10]]
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; IR: bb13:
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; IR-NEXT: [[MY_TMP14:%.*]] = phi i1 [ [[MY_TMP22]], [[BB3]] ], [ true, [[BB8]] ]
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@ -84,7 +82,7 @@ define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* noca
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; IR-NEXT: [[MY_TMP22]] = phi i1 [ false, [[BB16]] ], [ [[MY_TMP14]], [[BB13]] ]
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; IR-NEXT: br label [[BB9]]
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; IR: bb23:
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; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP3]])
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; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP6]])
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; IR-NEXT: ret void
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;
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bb:
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@ -28,7 +28,7 @@ define amdgpu_kernel void @loop_subregion_misordered(i32 addrspace(1)* %arg0) #0
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; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: LOOP.HEADER:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP7:%.*]], [[FLOW3:%.*]] ]
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP4:%.*]], [[FLOW3:%.*]] ]
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b
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; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]]
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@ -50,8 +50,8 @@ define amdgpu_kernel void @loop_subregion_misordered(i32 addrspace(1)* %arg0) #0
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; CHECK-NEXT: [[TMP25:%.*]] = mul nuw nsw i32 [[TMP24]], 52
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; CHECK-NEXT: br label [[INNER_LOOP:%.*]]
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; CHECK: Flow2:
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; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP9:%.*]], [[FLOW]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP11:%.*]], [[FLOW]] ]
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; CHECK-NEXT: [[TMP4]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP8:%.*]], [[FLOW]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP10:%.*]], [[FLOW]] ]
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; CHECK-NEXT: br i1 [[TMP5]], label [[END_ELSE_BLOCK:%.*]], label [[FLOW3]]
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; CHECK: INNER_LOOP:
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; CHECK-NEXT: [[INNER_LOOP_J:%.*]] = phi i32 [ [[INNER_LOOP_J_INC:%.*]], [[INNER_LOOP]] ], [ [[TMP25]], [[BB18:%.*]] ]
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@ -68,28 +68,26 @@ define amdgpu_kernel void @loop_subregion_misordered(i32 addrspace(1)* %arg0) #0
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; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[LOAD13]], true
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; CHECK-NEXT: br i1 [[TMP6]], label [[INCREMENT_I]], label [[FLOW1:%.*]]
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; CHECK: Flow3:
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; CHECK-NEXT: [[TMP7]] = phi i32 [ [[I_FINAL:%.*]], [[END_ELSE_BLOCK]] ], [ undef, [[FLOW2]] ]
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; CHECK-NEXT: [[TMP8:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK:%.*]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW2]] ]
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; CHECK-NEXT: br i1 [[TMP8]], label [[FLOW4:%.*]], label [[LOOP_HEADER]]
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; CHECK-NEXT: [[TMP7:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK:%.*]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW2]] ]
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; CHECK-NEXT: br i1 [[TMP7]], label [[FLOW4:%.*]], label [[LOOP_HEADER]]
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; CHECK: Flow4:
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; CHECK-NEXT: br i1 [[TMP10:%.*]], label [[BB64:%.*]], label [[RETURN:%.*]]
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; CHECK-NEXT: br i1 [[TMP9:%.*]], label [[BB64:%.*]], label [[RETURN:%.*]]
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; CHECK: bb64:
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; CHECK-NEXT: call void asm sideeffect "s_nop 42", "~{memory}"() #0
|
||||
; CHECK-NEXT: br label [[RETURN]]
|
||||
; CHECK: Flow:
|
||||
; CHECK-NEXT: [[TMP9]] = phi i32 [ [[TMP1]], [[FLOW1]] ], [ undef, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP10]] = phi i1 [ [[TMP2]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP11]] = phi i1 [ [[TMP3]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = phi i1 [ false, [[FLOW1]] ], [ true, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP12]], label [[BB18]], label [[FLOW2]]
|
||||
; CHECK-NEXT: [[TMP8]] = phi i32 [ [[TMP1]], [[FLOW1]] ], [ undef, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP9]] = phi i1 [ [[TMP2]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP10]] = phi i1 [ [[TMP3]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[FLOW1]] ], [ true, [[LOOP_HEADER]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP11]], label [[BB18]], label [[FLOW2]]
|
||||
; CHECK: INCREMENT_I:
|
||||
; CHECK-NEXT: [[INC_I]] = add i32 [[I]], 1
|
||||
; CHECK-NEXT: call void asm sideeffect "s_nop 0x1336
|
||||
; CHECK-NEXT: br label [[FLOW1]]
|
||||
; CHECK: END_ELSE_BLOCK:
|
||||
; CHECK-NEXT: [[I_FINAL]] = phi i32 [ [[TMP4]], [[FLOW2]] ]
|
||||
; CHECK-NEXT: call void asm sideeffect "s_nop 0x1337
|
||||
; CHECK-NEXT: [[CMP_END_ELSE_BLOCK]] = icmp eq i32 [[I_FINAL]], -1
|
||||
; CHECK-NEXT: [[CMP_END_ELSE_BLOCK]] = icmp eq i32 [[TMP4]], -1
|
||||
; CHECK-NEXT: br label [[FLOW3]]
|
||||
; CHECK: RETURN:
|
||||
; CHECK-NEXT: call void asm sideeffect "s_nop 0x99
|
||||
|
||||
Loading…
Reference in New Issue
Block a user