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AMDGPU/GlobalISel: Do a better job splitting 64-bit G_SEXT_INREG
We don't need to expand to full shifts for the > 32-bit case. This just switches to a sext_inreg of the high half.
This commit is contained in:
Matt Arsenault
parent
acf5f4aa9b
commit
d15b15865e
@ -1799,53 +1799,39 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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return;
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}
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case AMDGPU::G_SEXT_INREG: {
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const RegisterBank *SrcBank =
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OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
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// We can directly handle all 64-bit cases with s_bfe_i64.
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if (SrcBank == &AMDGPU::SGPRRegBank)
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break;
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SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
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if (SrcRegs.empty())
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break; // Nothing to repair
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const LLT S32 = LLT::scalar(32);
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Register DstReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(1).getReg();
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LLT Ty = MRI.getType(DstReg);
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if (Ty == S32)
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break;
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MachineIRBuilder B(MI);
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ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank);
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GISelObserverWrapper Observer(&O);
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B.setChangeObserver(Observer);
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// Don't use LegalizerHelper's narrowScalar. It produces unwanted G_SEXTs
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// we would need to further expand, and doesn't let us directly set the
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// result registers.
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SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
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int Amt = MI.getOperand(2).getImm();
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if (Amt <= 32) {
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// Don't use LegalizerHelper's narrowScalar. It produces unwanted G_SEXTs
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// we would need to further expand, and doesn't let us directly set the
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// result registers.
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SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
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SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
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if (SrcRegs.empty())
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split64BitValueForMapping(B, SrcRegs, S32, SrcReg);
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// Extend in the low bits and propagate the sign bit to the high half.
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auto ShiftAmt = B.buildConstant(S32, 31);
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if (Amt == 32) {
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// The low bits are unchanged.
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B.buildCopy(DstRegs[0], SrcRegs[0]);
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B.buildAShr(DstRegs[1], DstRegs[0], ShiftAmt);
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} else {
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// Extend in the low bits and propagate the sign bit to the high half.
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B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
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B.buildAShr(DstRegs[1], DstRegs[0], ShiftAmt);
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}
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B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
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} else {
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assert(empty(OpdMapper.getVRegs(0)) && empty(OpdMapper.getVRegs(1)));
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const LLT S64 = LLT::scalar(64);
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// This straddles two registers. Expand with 64-bit shifts.
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auto ShiftAmt = B.buildConstant(S32, 64 - Amt);
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auto Shl = B.buildShl(S64, SrcReg, ShiftAmt);
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B.buildAShr(DstReg, Shl, ShiftAmt);
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// The low bits are unchanged, and extend in the high bits.
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B.buildCopy(DstRegs[0], SrcRegs[0]);
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B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32);
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}
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Register DstReg = MI.getOperand(0).getReg();
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MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
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MI.eraseFromParent();
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return;
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@ -2965,7 +2951,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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case AMDGPU::G_ZEXT:
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case AMDGPU::G_SEXT:
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case AMDGPU::G_ANYEXT: {
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case AMDGPU::G_ANYEXT:
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case AMDGPU::G_SEXT_INREG: {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
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@ -2996,24 +2983,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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break;
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}
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case AMDGPU::G_SEXT_INREG: {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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Register Amt = MI.getOperand(2).getImm();
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unsigned Size = getSizeInBits(Dst, MRI, *TRI);
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unsigned BankID = getRegBank(Src, MRI, *TRI)->getID();
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if (Amt <= 32) {
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OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(BankID, Size);
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} else {
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// If we need to expand a 64 bit for the VALU, this will straddle two
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// registers. Just expand this with 64-bit shifts.
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OpdsMapping[0] = AMDGPU::getValueMapping(BankID, Size);
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}
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OpdsMapping[1] = OpdsMapping[0];
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break;
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}
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case AMDGPU::G_FCMP: {
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unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
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unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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@ -121,8 +121,8 @@ body: |
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; CHECK-LABEL: name: sext_inreg_v_s64_1
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 1
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
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; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
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@ -143,8 +143,8 @@ body: |
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; CHECK-LABEL: name: sext_inreg_v_s64_31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 31
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
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; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
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@ -165,8 +165,8 @@ body: |
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; CHECK-LABEL: name: sext_inreg_v_s64_32
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY1]], [[C]](s32)
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[ASHR]](s32)
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; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
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@ -186,12 +186,55 @@ body: |
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; CHECK-LABEL: name: sext_inreg_v_s64_33
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[COPY]], [[C]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[C]](s32)
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; CHECK: S_ENDPGM 0, implicit [[ASHR]](s64)
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY1]], 1
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[SEXT_INREG]](s32)
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; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_SEXT_INREG %0, 33
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S_ENDPGM 0, implicit %1
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...
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---
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name: sext_inreg_v_s64_35
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: sext_inreg_v_s64_35
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY1]], 3
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[SEXT_INREG]](s32)
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; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_SEXT_INREG %0, 35
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S_ENDPGM 0, implicit %1
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...
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---
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name: sext_inreg_v_s64_63
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: sext_inreg_v_s64_63
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY1]], 31
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[SEXT_INREG]](s32)
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; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_SEXT_INREG %0, 63
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S_ENDPGM 0, implicit %1
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...
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