From d15f8bd42f3802e82fcf911777a407fbe5e9a79e Mon Sep 17 00:00:00 2001 From: Changpeng Fang Date: Thu, 1 Feb 2018 18:41:33 +0000 Subject: [PATCH] AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature. Reviewers: Matt and Brian Differential Revision: https://reviews.llvm.org/D42548 llvm-svn: 323988 --- lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 6 ++++++ lib/Target/AMDGPU/BUFInstructions.td | 8 ++++---- test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll | 2 +- 6 files changed, 14 insertions(+), 8 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp index 9b9ec063864..ef8ee902453 100644 --- a/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp @@ -95,6 +95,12 @@ int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const { if (get(Opcode).TSFlags & SIInstrFlags::SDWA) Gen = ST.getGeneration() == AMDGPUSubtarget::GFX9 ? SIEncodingFamily::SDWA9 : SIEncodingFamily::SDWA; + // Adjust the encoding family to GFX80 for D16 buffer instructions when the + // subtarget has UnpackedD16VMem feature. + // TODO: remove this when we discard GFX80 encoding. + if (ST.hasUnpackedD16VMem() && (get(Opcode).TSFlags & SIInstrFlags::D16) + && !(get(Opcode).TSFlags & SIInstrFlags::MIMG)) + Gen = SIEncodingFamily::GFX80; int MCOp = AMDGPU::getMCOpcode(Opcode, Gen); diff --git a/lib/Target/AMDGPU/BUFInstructions.td b/lib/Target/AMDGPU/BUFInstructions.td index ceb596c7d40..a430ffd4615 100644 --- a/lib/Target/AMDGPU/BUFInstructions.td +++ b/lib/Target/AMDGPU/BUFInstructions.td @@ -672,7 +672,7 @@ defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Pseudo_Stores < "buffer_store_format_xyzw", VReg_128 >; -let SubtargetPredicate = HasUnpackedD16VMem in { +let SubtargetPredicate = HasUnpackedD16VMem, D16 = 1 in { defm BUFFER_LOAD_FORMAT_D16_X_gfx80 : MUBUF_Pseudo_Loads < "buffer_load_format_d16_x", VGPR_32 >; @@ -699,7 +699,7 @@ let SubtargetPredicate = HasUnpackedD16VMem in { >; } // End HasUnpackedD16VMem. -let SubtargetPredicate = HasPackedD16VMem in { +let SubtargetPredicate = HasPackedD16VMem, D16 = 1 in { defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Pseudo_Loads < "buffer_load_format_d16_x", VGPR_32 >; @@ -915,7 +915,7 @@ defm TBUFFER_STORE_FORMAT_XY : MTBUF_Pseudo_Stores <"tbuffer_store_format_xy", defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyz", VReg_128>; defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyzw", VReg_128>; -let SubtargetPredicate = HasUnpackedD16VMem in { +let SubtargetPredicate = HasUnpackedD16VMem, D16 = 1 in { defm TBUFFER_LOAD_FORMAT_D16_X_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_x", VGPR_32>; defm TBUFFER_LOAD_FORMAT_D16_XY_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xy", VReg_64>; defm TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xyz", VReg_96>; @@ -926,7 +926,7 @@ let SubtargetPredicate = HasUnpackedD16VMem in { defm TBUFFER_STORE_FORMAT_D16_XYZW_gfx80 : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_128>; } // End HasUnpackedD16VMem. -let SubtargetPredicate = HasPackedD16VMem in { +let SubtargetPredicate = HasPackedD16VMem, D16 = 1 in { defm TBUFFER_LOAD_FORMAT_D16_X : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_x", VGPR_32>; defm TBUFFER_LOAD_FORMAT_D16_XY : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xy", VGPR_32>; defm TBUFFER_LOAD_FORMAT_D16_XYZ : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xyz", VReg_64>; diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll index 43776728d5c..274a5b2f0a7 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll index bcaa600a483..5824161447f 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED -check-prefix=GFX81 %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED -check-prefix=GFX9 %s diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll index 96d698ee51c..8850acae1b9 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll index 6ccdc2d7f2c..0367bb25d45 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED -check-prefix=GFX81 %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED -check-prefix=GFX9 %s