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[AArch64][FIX] FPR16_lo for f16 indexed patterns.

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This commit is contained in:
Pavel Iliin 2020-04-23 22:03:42 +01:00
parent 30af881117
commit d17728f4fd
4 changed files with 16 additions and 6 deletions
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8
lib/Target/AArch64/AArch64InstrFormats.td
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@ -8073,9 +8073,9 @@ multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
(!cast<Instruction>(INST # "v8i16_indexed")
V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
(AArch64dup (f16 FPR16Op:$Rm)))),
(AArch64dup (f16 FPR16Op_lo:$Rm)))),
(!cast<Instruction>(INST # "v8i16_indexed") V128:$Rd, V128:$Rn,
(SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>;
(SUBREG_TO_REG (i32 0), FPR16Op_lo:$Rm, hsub), (i64 0))>;
def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
(AArch64duplane16 (v8f16 V128_lo:$Rm),
@ -8083,9 +8083,9 @@ multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
(!cast<Instruction>(INST # "v4i16_indexed")
V64:$Rd, V64:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
(AArch64dup (f16 FPR16Op:$Rm)))),
(AArch64dup (f16 FPR16Op_lo:$Rm)))),
(!cast<Instruction>(INST # "v4i16_indexed") V64:$Rd, V64:$Rn,
(SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>;
(SUBREG_TO_REG (i32 0), FPR16Op_lo:$Rm, hsub), (i64 0))>;
def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
(vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))),

2
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
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@ -231,6 +231,8 @@ AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
switch (RC.getID()) {
case AArch64::FPR8RegClassID:
case AArch64::FPR16RegClassID:
case AArch64::FPR16_loRegClassID:
case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
case AArch64::FPR32RegClassID:
case AArch64::FPR64RegClassID:
case AArch64::FPR64_loRegClassID:

1
lib/Target/AArch64/AArch64RegisterInfo.cpp
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@ -597,6 +597,7 @@ unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
case AArch64::FPR128_loRegClassID:
case AArch64::FPR64_loRegClassID:
case AArch64::FPR16_loRegClassID:
return 16;
}
}

11
lib/Target/AArch64/AArch64RegisterInfo.td
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@ -425,6 +425,9 @@ def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
def FPR16 : RegisterClass<"AArch64", [f16], 16, (sequence "H%u", 0, 31)> {
let Size = 16;
}
def FPR16_lo : RegisterClass<"AArch64", [f16], 16, (trunc FPR16, 16)> {
let Size = 16;
}
def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
v1i64, v4f16],
@ -648,6 +651,10 @@ def FPR16Op : RegisterOperand<FPR16, "printOperand"> {
let ParserMatchClass = FPRAsmOperand<"FPR16">;
}
def FPR16Op_lo : RegisterOperand<FPR16_lo, "printOperand"> {
let ParserMatchClass = FPRAsmOperand<"FPR16_lo">;
}
def FPR32Op : RegisterOperand<FPR32, "printOperand"> {
let ParserMatchClass = FPRAsmOperand<"FPR32">;
}
@ -671,11 +678,11 @@ def XSeqPairs : RegisterTuples<[sube64, subo64],
[(decimate (rotl GPR64, 0), 2),
(decimate (rotl GPR64, 1), 2)]>;
def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
(add WSeqPairs)>{
let Size = 64;
}
def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
(add XSeqPairs)>{
let Size = 128;
}