RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

[GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromReg

Browse Source 
Some minor cleanup.

This function in Utils does the same thing as `findMIFromReg`. It also looks
through copies, which `findMIFromReg` didn't.

Delete `findMIFromReg` and use `getOpcodeDef` instead. This only happens in
`tryOptVectorDup` right now.

Update opt-shuffle-splat to show that we can look through the copies now, too.

Differential Revision: https://reviews.llvm.org/D64520

llvm-svn: 365684
This commit is contained in:
Jessica Paquette 2019-07-10 18:46:56 +00:00
parent 16c02a7004
commit d177d58582
2 changed files with 25 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -190,17 +190,6 @@ private:
unsigned char OpFlags) const;
// Optimization methods.
// Helper function to check if a reg def is an MI with a given opcode and
// returns it if so.
MachineInstr *findMIFromReg(unsigned Reg, unsigned Opc,
MachineIRBuilder &MIB) const {
auto *Def = MIB.getMRI()->getVRegDef(Reg);
if (!Def || Def->getOpcode() != Opc)
return nullptr;
return Def;
}
bool tryOptVectorShuffle(MachineInstr &I) const;
bool tryOptVectorDup(MachineInstr &MI) const;
bool tryOptSelect(MachineInstr &MI) const;
@ -3325,12 +3314,12 @@ bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const {
// Begin matching the insert.
auto *InsMI =
findMIFromReg(I.getOperand(1).getReg(), G_INSERT_VECTOR_ELT, MIB);
getOpcodeDef(G_INSERT_VECTOR_ELT, I.getOperand(1).getReg(), MRI);
if (!InsMI)
return false;
// Match the undef vector operand.
auto *UndefMI =
findMIFromReg(InsMI->getOperand(1).getReg(), G_IMPLICIT_DEF, MIB);
getOpcodeDef(G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), MRI);
if (!UndefMI)
return false;
// Match the scalar being splatted.
@ -3342,7 +3331,7 @@ bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const {
return false;
// The shuffle's second operand doesn't matter if the mask is all zero.
auto *ZeroVec = findMIFromReg(I.getOperand(3).getReg(), G_BUILD_VECTOR, MIB);
auto *ZeroVec = getOpcodeDef(G_BUILD_VECTOR, I.getOperand(3).getReg(), MRI);
if (!ZeroVec)
return false;
int64_t Zero = 0;

22
test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
View File

@ -108,3 +108,25 @@ body: |
RET_ReallyLR implicit $q0
...
---
name: splat_2xf64_copies
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d0
; This test is exactly the same as splat_2xf64, except it adds two copies.
; These copies shouldn't get in the way of matching the dup pattern.
%0:fpr(s64) = COPY $d0
%2:fpr(<2 x s64>) = G_IMPLICIT_DEF
%6:fpr(<2 x s64>) = COPY %2
%3:gpr(s32) = G_CONSTANT i32 0
%5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32)
%1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s32)
%7:fpr(<2 x s64>) = COPY %1
%4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, %5(<2 x s32>)
$q0 = COPY %4(<2 x s64>)
RET_ReallyLR implicit $q0