RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity

[GlobalISel][TableGen] Fix seg fault for zero instruction

Browse Source 
Tablegen seg faulted when parsing a Pat where the destination part has
no output (zero instruction), due to a register class lookup using
nullptr.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D90829
This commit is contained in:
Gabriel Hjort Åkerlund 2020-11-24 07:12:54 +01:00 committed by Mikael Holmen
parent 162ba2cc55
commit d18a71ef85
2 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
test/TableGen/GlobalISelEmitter-zero-instr.td Normal file
View File

@ -0,0 +1,8 @@
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
// CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf
def : Pat<(zext (i16 (trunc i32:$src))),
(i32 $src)>;

4
utils/TableGen/GlobalISelEmitter.cpp
View File

@ -5086,9 +5086,9 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
if (Dst->isLeaf()) {
Record *RCDef = getInitValueAsRegClass(Dst->getLeafValue());
const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
if (RCDef) {
const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
// We need to replace the def and all its uses with the specified
// operand. However, we must also insert COPY's wherever needed.
// For now, emit a copy and let the register allocator clean up.