From d192bcd830de70b2a6ea141ced9c83f17bf6f090 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sat, 25 Apr 2020 15:58:40 -0700 Subject: [PATCH] [TableGen] Drop deprecated leading # operation (NOP) and replace ## with # --- include/llvm/IR/IntrinsicsSystemZ.td | 90 ++--- include/llvm/Target/TargetSelectionDAG.td | 40 +- lib/Target/AArch64/AArch64InstrFormats.td | 16 +- lib/Target/AMDGPU/EvergreenInstructions.td | 6 +- lib/Target/AMDGPU/VOP3PInstructions.td | 12 +- lib/Target/ARM/ARMInstrMVE.td | 2 +- lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 16 +- lib/Target/Hexagon/HexagonIntrinsics.td | 4 +- lib/Target/Hexagon/HexagonPseudo.td | 4 +- lib/Target/Mips/MipsRegisterInfo.td | 16 +- lib/Target/SystemZ/SystemZFeatures.td | 6 +- lib/Target/SystemZ/SystemZInstrFormats.td | 80 ++-- lib/Target/SystemZ/SystemZOperands.td | 60 +-- lib/Target/SystemZ/SystemZOperators.td | 2 +- lib/Target/SystemZ/SystemZPatterns.td | 4 +- lib/Target/SystemZ/SystemZRegisterInfo.td | 6 +- lib/Target/X86/X86InstrAVX512.td | 372 +++++++++--------- lib/Target/X86/X86InstrSSE.td | 30 +- 18 files changed, 383 insertions(+), 383 deletions(-) diff --git a/include/llvm/IR/IntrinsicsSystemZ.td b/include/llvm/IR/IntrinsicsSystemZ.td index 40d6ba17eaf..dd156a3dc3b 100644 --- a/include/llvm/IR/IntrinsicsSystemZ.td +++ b/include/llvm/IR/IntrinsicsSystemZ.td @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// class SystemZUnaryConv - : GCCBuiltin<"__builtin_s390_" ## name>, + : GCCBuiltin<"__builtin_s390_" # name>, Intrinsic<[result], [arg], [IntrNoMem]>; class SystemZUnary @@ -24,14 +24,14 @@ class SystemZUnaryCC : SystemZUnaryConvCC; class SystemZBinaryConv - : GCCBuiltin<"__builtin_s390_" ## name>, + : GCCBuiltin<"__builtin_s390_" # name>, Intrinsic<[result], [arg, arg], [IntrNoMem]>; class SystemZBinary : SystemZBinaryConv; class SystemZBinaryInt - : GCCBuiltin<"__builtin_s390_" ## name>, + : GCCBuiltin<"__builtin_s390_" # name>, Intrinsic<[type], [type, llvm_i32_ty], [IntrNoMem]>; class SystemZBinaryConvCC @@ -45,7 +45,7 @@ class SystemZBinaryCC : SystemZBinaryConvCC; class SystemZTernaryConv - : GCCBuiltin<"__builtin_s390_" ## name>, + : GCCBuiltin<"__builtin_s390_" # name>, Intrinsic<[result], [arg, arg, result], [IntrNoMem]>; class SystemZTernaryConvCC @@ -55,7 +55,7 @@ class SystemZTernary : SystemZTernaryConv; class SystemZTernaryInt - : GCCBuiltin<"__builtin_s390_" ## name>, + : GCCBuiltin<"__builtin_s390_" # name>, Intrinsic<[type], [type, type, llvm_i32_ty], [IntrNoMem, ImmArg<2>]>; class SystemZTernaryIntCC @@ -63,7 +63,7 @@ class SystemZTernaryIntCC [IntrNoMem, ImmArg<2>]>; class SystemZQuaternaryInt - : GCCBuiltin<"__builtin_s390_" ## name>, + : GCCBuiltin<"__builtin_s390_" # name>, Intrinsic<[type], [type, type, type, llvm_i32_ty], [IntrNoMem, ImmArg<3>]>; @@ -72,25 +72,25 @@ class SystemZQuaternaryIntCC [IntrNoMem, ImmArg<3>]>; multiclass SystemZUnaryExtBHF { - def b : SystemZUnaryConv; - def h : SystemZUnaryConv; - def f : SystemZUnaryConv; + def b : SystemZUnaryConv; + def h : SystemZUnaryConv; + def f : SystemZUnaryConv; } multiclass SystemZUnaryExtBHWF { - def b : SystemZUnaryConv; - def hw : SystemZUnaryConv; - def f : SystemZUnaryConv; + def b : SystemZUnaryConv; + def hw : SystemZUnaryConv; + def f : SystemZUnaryConv; } multiclass SystemZUnaryBHF { - def b : SystemZUnary; - def h : SystemZUnary; - def f : SystemZUnary; + def b : SystemZUnary; + def h : SystemZUnary; + def f : SystemZUnary; } multiclass SystemZUnaryBHFG : SystemZUnaryBHF { - def g : SystemZUnary; + def g : SystemZUnary; } multiclass SystemZUnaryCCBHF { @@ -100,9 +100,9 @@ multiclass SystemZUnaryCCBHF { } multiclass SystemZBinaryTruncHFG { - def h : SystemZBinaryConv; - def f : SystemZBinaryConv; - def g : SystemZBinaryConv; + def h : SystemZBinaryConv; + def f : SystemZBinaryConv; + def g : SystemZBinaryConv; } multiclass SystemZBinaryTruncCCHFG { @@ -112,30 +112,30 @@ multiclass SystemZBinaryTruncCCHFG { } multiclass SystemZBinaryExtBHF { - def b : SystemZBinaryConv; - def h : SystemZBinaryConv; - def f : SystemZBinaryConv; + def b : SystemZBinaryConv; + def h : SystemZBinaryConv; + def f : SystemZBinaryConv; } multiclass SystemZBinaryExtBHFG : SystemZBinaryExtBHF { - def g : SystemZBinaryConv; + def g : SystemZBinaryConv; } multiclass SystemZBinaryBHF { - def b : SystemZBinary; - def h : SystemZBinary; - def f : SystemZBinary; + def b : SystemZBinary; + def h : SystemZBinary; + def f : SystemZBinary; } multiclass SystemZBinaryBHFG : SystemZBinaryBHF { - def g : SystemZBinary; + def g : SystemZBinary; } multiclass SystemZBinaryIntBHFG { - def b : SystemZBinaryInt; - def h : SystemZBinaryInt; - def f : SystemZBinaryInt; - def g : SystemZBinaryInt; + def b : SystemZBinaryInt; + def h : SystemZBinaryInt; + def f : SystemZBinaryInt; + def g : SystemZBinaryInt; } multiclass SystemZBinaryCCBHF { @@ -152,25 +152,25 @@ multiclass SystemZCompareBHFG { } multiclass SystemZTernaryExtBHF { - def b : SystemZTernaryConv; - def h : SystemZTernaryConv; - def f : SystemZTernaryConv; + def b : SystemZTernaryConv; + def h : SystemZTernaryConv; + def f : SystemZTernaryConv; } multiclass SystemZTernaryExtBHFG : SystemZTernaryExtBHF { - def g : SystemZTernaryConv; + def g : SystemZTernaryConv; } multiclass SystemZTernaryBHF { - def b : SystemZTernary; - def h : SystemZTernary; - def f : SystemZTernary; + def b : SystemZTernary; + def h : SystemZTernary; + def f : SystemZTernary; } multiclass SystemZTernaryIntBHF { - def b : SystemZTernaryInt; - def h : SystemZTernaryInt; - def f : SystemZTernaryInt; + def b : SystemZTernaryInt; + def h : SystemZTernaryInt; + def f : SystemZTernaryInt; } multiclass SystemZTernaryIntCCBHF { @@ -180,14 +180,14 @@ multiclass SystemZTernaryIntCCBHF { } multiclass SystemZQuaternaryIntBHF { - def b : SystemZQuaternaryInt; - def h : SystemZQuaternaryInt; - def f : SystemZQuaternaryInt; + def b : SystemZQuaternaryInt; + def h : SystemZQuaternaryInt; + def f : SystemZQuaternaryInt; } multiclass SystemZQuaternaryIntBHFG : SystemZQuaternaryIntBHF { - def g : SystemZQuaternaryInt; + def g : SystemZQuaternaryInt; } multiclass SystemZQuaternaryIntCCBHF { diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index da26b71fcfc..1f5cfba41a3 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -1421,56 +1421,56 @@ def any_uint_to_fp : PatFrags<(ops node:$src), (uint_to_fp node:$src)]>; multiclass binary_atomic_op_ord { - def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), - (!cast(#NAME) node:$ptr, node:$val)> { + def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), + (!cast(NAME) node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingMonotonic = 1; } - def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), - (!cast(#NAME) node:$ptr, node:$val)> { + def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), + (!cast(NAME) node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingAcquire = 1; } - def #NAME#_release : PatFrag<(ops node:$ptr, node:$val), - (!cast(#NAME) node:$ptr, node:$val)> { + def NAME#_release : PatFrag<(ops node:$ptr, node:$val), + (!cast(NAME) node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingRelease = 1; } - def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), - (!cast(#NAME) node:$ptr, node:$val)> { + def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), + (!cast(NAME) node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingAcquireRelease = 1; } - def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), - (!cast(#NAME) node:$ptr, node:$val)> { + def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), + (!cast(NAME) node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingSequentiallyConsistent = 1; } } multiclass ternary_atomic_op_ord { - def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), - (!cast(#NAME) node:$ptr, node:$cmp, node:$val)> { + def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), + (!cast(NAME) node:$ptr, node:$cmp, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingMonotonic = 1; } - def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), - (!cast(#NAME) node:$ptr, node:$cmp, node:$val)> { + def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), + (!cast(NAME) node:$ptr, node:$cmp, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingAcquire = 1; } - def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), - (!cast(#NAME) node:$ptr, node:$cmp, node:$val)> { + def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), + (!cast(NAME) node:$ptr, node:$cmp, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingRelease = 1; } - def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), - (!cast(#NAME) node:$ptr, node:$cmp, node:$val)> { + def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), + (!cast(NAME) node:$ptr, node:$cmp, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingAcquireRelease = 1; } - def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), - (!cast(#NAME) node:$ptr, node:$cmp, node:$val)> { + def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), + (!cast(NAME) node:$ptr, node:$cmp, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingSequentiallyConsistent = 1; } diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 9bc8f507449..a06394a2898 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -6736,12 +6736,12 @@ multiclass SIMDThreeScalarHSTied opc, string asm, multiclass SIMDFPThreeScalar opc, string asm, SDPatternOperator OpNode = null_frag> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { - def #NAME#64 : BaseSIMDThreeScalar; - def #NAME#32 : BaseSIMDThreeScalar; let Predicates = [HasNEON, HasFullFP16] in { - def #NAME#16 : BaseSIMDThreeScalar; } // Predicates = [HasNEON, HasFullFP16] } @@ -6753,12 +6753,12 @@ multiclass SIMDFPThreeScalar opc, string asm, multiclass SIMDThreeScalarFPCmp opc, string asm, SDPatternOperator OpNode = null_frag> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { - def #NAME#64 : BaseSIMDThreeScalar; - def #NAME#32 : BaseSIMDThreeScalar; let Predicates = [HasNEON, HasFullFP16] in { - def #NAME#16 : BaseSIMDThreeScalar; } // Predicates = [HasNEON, HasFullFP16] } @@ -7291,7 +7291,7 @@ class SIMDInsMainMovAlias; class SIMDInsElementMovAlias - : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" # + : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" # "|" # size #"\t$dst$idx, $src$idx2}", (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>; @@ -7532,7 +7532,7 @@ class BaseSIMDScalarCPY - : InstAlias; diff --git a/lib/Target/AMDGPU/EvergreenInstructions.td b/lib/Target/AMDGPU/EvergreenInstructions.td index 1b4bbf1d089..97104a242d8 100644 --- a/lib/Target/AMDGPU/EvergreenInstructions.td +++ b/lib/Target/AMDGPU/EvergreenInstructions.td @@ -69,11 +69,11 @@ multiclass RAT_ATOMIC op_ret, bits<6> op_noret, string name> { def _RTN: CF_MEM_RAT ; + name # "_RTN" # " $rw_gpr, $index_gpr", [] >; def _NORET: CF_MEM_RAT ; + name # " $rw_gpr, $index_gpr", [] >; } } @@ -572,7 +572,7 @@ class R600_LDS_1A1D_NORET lds_op, string name, list pattern> : } class R600_LDS_1A1D_RET lds_op, string name, list pattern> : - R600_LDS_1A1D { + R600_LDS_1A1D { let BaseOp = name; let usesCustomInserter = 1; diff --git a/lib/Target/AMDGPU/VOP3PInstructions.td b/lib/Target/AMDGPU/VOP3PInstructions.td index 517c7fe680a..25075e17984 100644 --- a/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/lib/Target/AMDGPU/VOP3PInstructions.td @@ -210,7 +210,7 @@ foreach Type = ["I", "U"] in foreach Index = 0-3 in { // Defines patterns that extract each Index'ed 8bit from an unsigned // 32bit scalar value; - def #Type#Index#"_8bit" : Extract; + def Type#Index#"_8bit" : Extract; // Defines multiplication patterns where the multiplication is happening on each // Index'ed 8bit of a 32bit scalar value. @@ -218,8 +218,8 @@ foreach Type = ["I", "U"] in def Mul#Type#_Elt#Index : PatFrag< (ops node:$src0, node:$src1), (!cast(!if (!eq (Type, "I"), AMDGPUmul_i24_oneuse, AMDGPUmul_u24_oneuse)) - (!cast(#Type#Index#"_8bit") node:$src0), - (!cast(#Type#Index#"_8bit") node:$src1))>; + (!cast(Type#Index#"_8bit") node:$src0), + (!cast(Type#Index#"_8bit") node:$src1))>; } // Different variants of dot8 patterns cause a huge increase in the compile time. @@ -238,15 +238,15 @@ foreach Type = ["I", "U"] in foreach Index = 0-7 in { // Defines patterns that extract each Index'ed 4bit from an unsigned // 32bit scalar value; - def #Type#Index#"_4bit" : Extract; + def Type#Index#"_4bit" : Extract; // Defines multiplication patterns where the multiplication is happening on each // Index'ed 8bit of a 32bit scalar value. def Mul#Type#Index#"_4bit" : PatFrag< (ops node:$src0, node:$src1), (!cast(!if (!eq (Type, "I"), NonACAMDGPUmul_i24_oneuse, NonACAMDGPUmul_u24_oneuse)) - (!cast(#Type#Index#"_4bit") node:$src0), - (!cast(#Type#Index#"_4bit") node:$src1))>; + (!cast(Type#Index#"_4bit") node:$src0), + (!cast(Type#Index#"_4bit") node:$src1))>; } class UDot2Pat : GCNPat < diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td index 3da4579be39..f14c00499be 100644 --- a/lib/Target/ARM/ARMInstrMVE.td +++ b/lib/Target/ARM/ARMInstrMVE.td @@ -285,7 +285,7 @@ class MVEVectorVTInfo(LaneBits)); // The suffix used on an instruction that mentions the whole type. - string Suffix = suffixletter ## BitsSuffix; + string Suffix = suffixletter # BitsSuffix; // The letter part of the suffix only. string SuffixLetter = suffixletter; diff --git a/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td index e9e009624ff..0143d6f44d8 100644 --- a/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td +++ b/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td @@ -1788,21 +1788,21 @@ def: Pat<(int_hexagon_F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs: // V60 HVX Instructions. def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; + (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vS32b_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; + (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; + (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vS32b_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; + (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; + (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; + (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; + (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; + (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index df6b63c19fa..10d0261a95d 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -205,12 +205,12 @@ def: T_stc_pat; multiclass MaskedStore { def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, + (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[UseHVX]>; def : Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, + (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[UseHVX]>; } diff --git a/lib/Target/Hexagon/HexagonPseudo.td b/lib/Target/Hexagon/HexagonPseudo.td index 61f0767dc28..20c93957758 100644 --- a/lib/Target/Hexagon/HexagonPseudo.td +++ b/lib/Target/Hexagon/HexagonPseudo.td @@ -112,7 +112,7 @@ let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, opExtendable = 0, hasSideEffects = 0 in class LOOP_iBase : InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2), - #mnemonic#"($offset,#$src2)", + mnemonic#"($offset,#$src2)", [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon { bits<9> offset; bits<10> src2; @@ -132,7 +132,7 @@ let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, opExtendable = 0, hasSideEffects = 0 in class LOOP_rBase : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2), - #mnemonic#"($offset,$src2)", + mnemonic#"($offset,$src2)", [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon { bits<9> offset; bits<5> src2; diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 8a6279da46b..7d4dcca89e3 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -194,23 +194,23 @@ let Namespace = "Mips" in { // FP control registers. foreach I = 0-31 in - def FCR#I : MipsReg<#I, ""#I>; + def FCR#I : MipsReg; // FP condition code registers. foreach I = 0-7 in - def FCC#I : MipsReg<#I, "fcc"#I>; + def FCC#I : MipsReg; // COP0 registers. foreach I = 0-31 in - def COP0#I : MipsReg<#I, ""#I>; + def COP0#I : MipsReg; // COP2 registers. foreach I = 0-31 in - def COP2#I : MipsReg<#I, ""#I>; + def COP2#I : MipsReg; // COP3 registers. foreach I = 0-31 in - def COP3#I : MipsReg<#I, ""#I>; + def COP3#I : MipsReg; // PC register def PC : Register<"pc">; @@ -222,11 +222,11 @@ let Namespace = "Mips" in { def HWR3 : MipsReg<3, "hwr_ccres">; foreach I = 4-31 in - def HWR#I : MipsReg<#I, ""#I>; + def HWR#I : MipsReg; // Accum registers foreach I = 0-3 in - def AC#I : ACCReg<#I, "ac"#I, + def AC#I : ACCReg("LO"#I), !cast("HI"#I)]>; def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; @@ -262,7 +262,7 @@ let Namespace = "Mips" in { // These registers do not exist, but instructions like `cfcmsa` // and `ctcmsa` allows to specify them. foreach I = 8-31 in - def MSA#I : MipsReg<#I, ""#I>; + def MSA#I : MipsReg; // Octeon multiplier and product registers def MPL0 : MipsReg<0, "mpl0">; diff --git a/lib/Target/SystemZ/SystemZFeatures.td b/lib/Target/SystemZ/SystemZFeatures.td index 07975bcdd8f..28f58cb310a 100644 --- a/lib/Target/SystemZ/SystemZFeatures.td +++ b/lib/Target/SystemZ/SystemZFeatures.td @@ -11,12 +11,12 @@ //===----------------------------------------------------------------------===// class SystemZFeature - : Predicate<"Subtarget->has"##intname##"()">, + : Predicate<"Subtarget->has"#intname#"()">, AssemblerPredicate, - SubtargetFeature; + SubtargetFeature; class SystemZMissingFeature - : Predicate<"!Subtarget->has"##intname##"()">; + : Predicate<"!Subtarget->has"#intname#"()">; class SystemZFeatureList x> { list List = x; diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index 9d5697d1ec6..bb6e57d7a8c 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -2334,49 +2334,49 @@ class FixedCmpBranchRSYb opcode, class BranchUnaryRI opcode, RegisterOperand cls> : InstRIb { + mnemonic#"\t$R1, $RI2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } class BranchUnaryRIL opcode, RegisterOperand cls> : InstRILb { + mnemonic#"\t$R1, $RI2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } class BranchUnaryRR opcode, RegisterOperand cls> : InstRR { + mnemonic#"\t$R1, $R2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } class BranchUnaryRRE opcode, RegisterOperand cls> : InstRRE { + mnemonic#"\t$R1, $R2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } class BranchUnaryRX opcode, RegisterOperand cls> : InstRXa { + mnemonic#"\t$R1, $XBD2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } class BranchUnaryRXY opcode, RegisterOperand cls> : InstRXYa { + mnemonic#"\t$R1, $XBD2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } class BranchBinaryRSI opcode, RegisterOperand cls> : InstRSI { + mnemonic#"\t$R1, $R3, $RI2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } @@ -2384,7 +2384,7 @@ class BranchBinaryRSI opcode, RegisterOperand cls> class BranchBinaryRIEe opcode, RegisterOperand cls> : InstRIEe { + mnemonic#"\t$R1, $R3, $RI2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } @@ -2392,7 +2392,7 @@ class BranchBinaryRIEe opcode, RegisterOperand cls> class BranchBinaryRS opcode, RegisterOperand cls> : InstRSa { + mnemonic#"\t$R1, $R3, $BD2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } @@ -2400,7 +2400,7 @@ class BranchBinaryRS opcode, RegisterOperand cls> class BranchBinaryRSY opcode, RegisterOperand cls> : InstRSYa { + mnemonic#"\t$R1, $R3, $BD2", []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } @@ -2421,7 +2421,7 @@ class LoadMultipleRSY opcode, RegisterOperand cls, multiclass LoadMultipleRSPair rsOpcode, bits<16> rsyOpcode, RegisterOperand cls> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : LoadMultipleRS; let DispSize = "20" in @@ -2487,7 +2487,7 @@ class StoreRXY opcode, SDPatternOperator operator, multiclass StoreRXPair rxOpcode, bits<16> rxyOpcode, SDPatternOperator operator, RegisterOperand cls, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : StoreRX; let DispSize = "20" in @@ -2567,7 +2567,7 @@ class StoreMultipleRSY opcode, RegisterOperand cls, multiclass StoreMultipleRSPair rsOpcode, bits<16> rsyOpcode, RegisterOperand cls> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : StoreMultipleRS; let DispSize = "20" in @@ -2888,7 +2888,7 @@ class UnaryRXY opcode, SDPatternOperator operator, multiclass UnaryRXPair rxOpcode, bits<16> rxyOpcode, SDPatternOperator operator, RegisterOperand cls, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : UnaryRX; let DispSize = "20" in @@ -2952,7 +2952,7 @@ multiclass UnaryExtraVRRaSPair opcode, def : InstAlias(NAME) tr1.op:$V1, tr2.op:$V2, 0)>; let Defs = [CC] in - def S : UnaryVRRa; } @@ -2996,17 +2996,17 @@ multiclass UnaryVRXAlign opcode> { class SideEffectBinaryRX opcode, RegisterOperand cls> : InstRXa; + mnemonic#"\t$R1, $XBD2", []>; class SideEffectBinaryRXY opcode, RegisterOperand cls> : InstRXYa; + mnemonic#"\t$R1, $XBD2", []>; class SideEffectBinaryRILPC opcode, RegisterOperand cls> : InstRILb { + mnemonic#"\t$R1, $RI2", []> { // We want PC-relative addresses to be tried ahead of BD and BDX addresses. // However, BDXs have two extra operands and are therefore 6 units more // complex. @@ -3049,16 +3049,16 @@ class SideEffectBinarySIL opcode, class SideEffectBinarySSa opcode> : InstSSa; + mnemonic#"\t$BDL1, $BD2", []>; class SideEffectBinarySSb opcode> : InstSSb; + mnemonic#"\t$BDL1, $BDL2", []>; class SideEffectBinarySSf opcode> : InstSSf; + mnemonic#"\t$BD1, $BDL2", []>; class SideEffectBinarySSE opcode> : InstSSE opcode1, bits<16> opcode2, ImmOpWithPattern imm> { let NumOpsKey = mnemonic in { let NumOpsValue = "3" in - def K : BinaryRIE, + def K : BinaryRIE, Requires<[FeatureDistinctOps]>; let NumOpsValue = "2" in def "" : BinaryRI; @@ -3384,7 +3384,7 @@ multiclass BinaryRSAndK opcode1, bits<16> opcode2, SDPatternOperator operator, RegisterOperand cls> { let NumOpsKey = mnemonic in { let NumOpsValue = "3" in - def K : BinaryRSY, + def K : BinaryRSY, Requires<[FeatureDistinctOps]>; let NumOpsValue = "2" in def "" : BinaryRS; @@ -3456,7 +3456,7 @@ class BinaryRXY opcode, SDPatternOperator operator, multiclass BinaryRXPair rxOpcode, bits<16> rxyOpcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : BinaryRX; @@ -3487,7 +3487,7 @@ class BinarySIY opcode, SDPatternOperator operator, multiclass BinarySIPair siOpcode, bits<16> siyOpcode, SDPatternOperator operator, Operand imm> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : BinarySI; let DispSize = "20" in @@ -3583,7 +3583,7 @@ multiclass BinaryVRRbSPair opcode, def "" : BinaryVRRb; let Defs = [CC] in - def S : BinaryVRRb; } @@ -3612,7 +3612,7 @@ multiclass BinaryExtraVRRbSPair opcode, (!cast(NAME) tr1.op:$V1, tr2.op:$V2, tr2.op:$V3, 0)>; let Defs = [CC] in - def S : BinaryVRRb; + def S : BinaryVRRb; } multiclass BinaryExtraVRRbSPairGeneric opcode> { @@ -3663,7 +3663,7 @@ multiclass BinaryVRRcSPair opcode, def "" : BinaryVRRc; let Defs = [CC] in - def S : BinaryVRRc; } @@ -3760,7 +3760,7 @@ class StoreBinaryRSY opcode, RegisterOperand cls, multiclass StoreBinaryRSPair rsOpcode, bits<16> rsyOpcode, RegisterOperand cls, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : StoreBinaryRS; let DispSize = "20" in @@ -3900,7 +3900,7 @@ class CompareRXY opcode, SDPatternOperator operator, multiclass CompareRXPair rxOpcode, bits<16> rxyOpcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : CompareRX; @@ -3928,7 +3928,7 @@ class CompareRSY opcode, RegisterOperand cls, multiclass CompareRSPair rsOpcode, bits<16> rsyOpcode, RegisterOperand cls, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : CompareRS; let DispSize = "20" in @@ -3939,7 +3939,7 @@ multiclass CompareRSPair rsOpcode, bits<16> rsyOpcode, class CompareSSb opcode> : InstSSb { + mnemonic#"\t$BDL1, $BDL2", []> { let isCompare = 1; let mayLoad = 1; } @@ -4051,7 +4051,7 @@ class TestVRRg opcode> class SideEffectTernarySSc opcode> : InstSSc; + mnemonic#"\t$BDL1, $BD2, $I3", []>; class SideEffectTernaryRRFa opcode, RegisterOperand cls1, RegisterOperand cls2, @@ -4187,7 +4187,7 @@ class TernaryRSY opcode, RegisterOperand cls, multiclass TernaryRSPair rsOpcode, bits<16> rsyOpcode, RegisterOperand cls, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : TernaryRS; let DispSize = "20" in @@ -4311,7 +4311,7 @@ multiclass TernaryOptVRRbSPair opcode, (!cast(NAME) tr1.op:$V1, tr2.op:$V2, tr2.op:$V3, 0)>; let Defs = [CC] in - def S : TernaryVRRb; def : InstAlias(NAME#"S") tr1.op:$V1, tr2.op:$V2, @@ -4544,7 +4544,7 @@ multiclass QuaternaryOptVRRdSPair opcode, (!cast(NAME) tr1.op:$V1, tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, 0)>; let Defs = [CC] in - def S : QuaternaryVRRd; def : InstAlias opcode, SDPatternOperator operator, multiclass CmpSwapRSPair rsOpcode, bits<16> rsyOpcode, SDPatternOperator operator, RegisterOperand cls> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { let DispSize = "12" in def "" : CmpSwapRS; let DispSize = "20" in @@ -4658,13 +4658,13 @@ class RotateSelectRIEf opcode, RegisterOperand cls1, class PrefetchRXY opcode, SDPatternOperator operator> : InstRXYb; class PrefetchRILPC opcode, SDPatternOperator operator> : InstRILc { // We want PC-relative addresses to be tried ahead of BD and BDX addresses. // However, BDXs have two extra operands and are therefore 6 units more @@ -5085,7 +5085,7 @@ multiclass BinaryRXPairAndPseudo rxOpcode, bits<16> rxyOpcode, SDPatternOperator operator, RegisterOperand cls, SDPatternOperator load, bits<5> bytes> { - let DispKey = mnemonic ## #cls in { + let DispKey = mnemonic # cls in { def "" : BinaryRX { let DispSize = "12"; diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index bd40f6d7bf4..a883daad73e 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -22,8 +22,8 @@ class ImmediateTLSAsmOperand } class ImmediateOp : Operand { - let PrintMethod = "print"##asmop##"Operand"; - let DecoderMethod = "decode"##asmop##"Operand"; + let PrintMethod = "print"#asmop#"Operand"; + let DecoderMethod = "decode"#asmop#"Operand"; let ParserMatchClass = !cast(asmop); let OperandType = "OPERAND_IMMEDIATE"; } @@ -52,14 +52,14 @@ multiclass Immediate { // Constructs an asm operand for a PC-relative address. SIZE says how // many bits there are. -class PCRelAsmOperand : ImmediateAsmOperand<"PCRel"##size> { +class PCRelAsmOperand : ImmediateAsmOperand<"PCRel"#size> { let PredicateMethod = "isImm"; - let ParserMethod = "parsePCRel"##size; + let ParserMethod = "parsePCRel"#size; } class PCRelTLSAsmOperand - : ImmediateTLSAsmOperand<"PCRelTLS"##size> { + : ImmediateTLSAsmOperand<"PCRelTLS"#size> { let PredicateMethod = "isImmTLS"; - let ParserMethod = "parsePCRelTLS"##size; + let ParserMethod = "parsePCRelTLS"#size; } // Constructs an operand for a PC-relative address with address type VT. @@ -92,9 +92,9 @@ class PCRelAddress class AddressAsmOperand : AsmOperandClass { - let Name = format##bitsize##"Disp"##dispsize##length; - let ParserMethod = "parse"##format##bitsize; - let RenderMethod = "add"##format##"Operands"; + let Name = format#bitsize#"Disp"#dispsize#length; + let ParserMethod = "parse"#format#bitsize; + let RenderMethod = "add"#format#"Operands"; } // Constructs an instruction operand for an addressing mode. FORMAT, @@ -103,15 +103,15 @@ class AddressAsmOperand - : Operand("i"##bitsize)> { - let PrintMethod = "print"##format##"Operand"; - let EncoderMethod = "get"##format##dispsize##length##"Encoding"; + : Operand("i"#bitsize)> { + let PrintMethod = "print"#format#"Operand"; + let EncoderMethod = "get"#format#dispsize#length#"Encoding"; let DecoderMethod = - "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; + "decode"#format#bitsize#"Disp"#dispsize#length#"Operand"; let OperandType = "OPERAND_MEMORY"; let MIOperandInfo = operands; let ParserMatchClass = - !cast(format##bitsize##"Disp"##dispsize##length); + !cast(format#bitsize#"Disp"#dispsize#length); } // Constructs both a DAG pattern and instruction operand for an addressing mode. @@ -126,45 +126,45 @@ class AddressOperand - : ComplexPattern("i"##bitsize), numops, - "select"##seltype##dispsize##suffix##length, + : ComplexPattern("i"#bitsize), numops, + "select"#seltype#dispsize#suffix#length, [add, sub, or, frameindex, z_adjdynalloc]>, AddressOperand; // An addressing mode with a base and displacement but no index. class BDMode : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize))>; // An addressing mode with a base, displacement and index. class BDXMode : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), - !cast("ADDR"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), + !cast("ADDR"#bitsize))>; // A BDMode paired with an immediate length operand of LENSIZE bits. class BDLMode - : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), - !cast("imm"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), + !cast("imm"#bitsize))>; // A BDMode paired with a register length operand. class BDRMode : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), - !cast("GR"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), + !cast("GR"#bitsize))>; // An addressing mode with a base, displacement and a vector index. class BDVMode : AddressOperand("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), !cast("VR128"))>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/SystemZ/SystemZOperators.td b/lib/Target/SystemZ/SystemZOperators.td index a6a72903e57..852c6282be6 100644 --- a/lib/Target/SystemZ/SystemZOperators.td +++ b/lib/Target/SystemZ/SystemZOperators.td @@ -374,7 +374,7 @@ def z_vstrsz_cc : SDNode<"SystemZISD::VSTRSZ_CC", def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvIntCC>; class AtomicWOp - : SDNode<"SystemZISD::"##name, profile, + : SDNode<"SystemZISD::"#name, profile, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td index 77fee342291..e3190eddb9f 100644 --- a/lib/Target/SystemZ/SystemZPatterns.td +++ b/lib/Target/SystemZ/SystemZPatterns.td @@ -57,10 +57,10 @@ multiclass RMWIByte { - def : Pat<(!cast("or_as_"##type) + def : Pat<(!cast("or_as_"#type) cls:$src1, (load mode:$src2)), (insn cls:$src1, mode:$src2)>; - def : Pat<(!cast("or_as_rev"##type) + def : Pat<(!cast("or_as_rev"#type) (load mode:$src2), cls:$src1), (insn cls:$src1, mode:$src2)>; } diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index 3567b0f3acf..a85862e6274 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -35,15 +35,15 @@ multiclass SystemZRegClass types, int size, dag regList, bit allocatable = 1> { def AsmOperand : AsmOperandClass { let Name = name; - let ParserMethod = "parse"##name; + let ParserMethod = "parse"#name; let RenderMethod = "addRegOperands"; } let isAllocatable = allocatable in def Bit : RegisterClass<"SystemZ", types, size, regList> { let Size = size; } - def "" : RegisterOperand(name##"Bit")> { - let ParserMatchClass = !cast(name##"AsmOperand"); + def "" : RegisterOperand(name#"Bit")> { + let ParserMatchClass = !cast(name#"AsmOperand"); } } diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index b4d007d4d8c..a3474eed1e3 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -1313,7 +1313,7 @@ multiclass avx512_int_broadcast_reg opc, SchedWrite SchedRR, let ExeDomain = _.ExeDomain in defm rr : AVX512_maskable, T8PD, EVEX, Sched<[SchedRR]>; } @@ -1326,7 +1326,7 @@ multiclass avx512_int_broadcastbw_reg opc, string Name, SchedWrite Sched (outs _.RC:$dst), (ins GR32:$src), !con((ins _.RC:$src0, _.KRCWM:$mask), (ins GR32:$src)), !con((ins _.KRCWM:$mask), (ins GR32:$src)), - "vpbroadcast"##_.Suffix, "$src", "$src", [], [], [], + "vpbroadcast"#_.Suffix, "$src", "$src", [], [], [], "$src0 = $dst">, T8PD, EVEX, Sched<[SchedRR]>; def : Pat <(_.VT (OpNode SrcRC:$src)), @@ -2626,13 +2626,13 @@ multiclass avx512_scalar_fpclass opc, string OpcodeStr, let Predicates = [prd], ExeDomain = _.ExeDomain, Uses = [MXCSR] in { def rr : AVX512, Sched<[sched]>; def rrk : AVX512 opc, string OpcodeStr, EVEX_K, Sched<[sched]>; def rm : AVX512 opc, string OpcodeStr, Sched<[sched.Folded, sched.ReadAfterFold]>; def rmk : AVX512 opc, string OpcodeStr, let ExeDomain = _.ExeDomain, Uses = [MXCSR] in { def rr : AVX512, Sched<[sched]>; def rrk : AVX512 opc, string OpcodeStr, EVEX_K, Sched<[sched]>; def rm : AVX512 opc, string OpcodeStr, Sched<[sched.Folded, sched.ReadAfterFold]>; def rmk : AVX512 opc, string OpcodeStr, EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>; def rmb : AVX512, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>; def rmbk : AVX512, @@ -3045,7 +3045,7 @@ multiclass avx512_mask_unpck; def : Pat<(Dst.KVT (concat_vectors Src.KRC:$src1, Src.KRC:$src2)), - (!cast(NAME##rr) Src.KRC:$src2, Src.KRC:$src1)>; + (!cast(NAME#rr) Src.KRC:$src2, Src.KRC:$src1)>; } } @@ -3281,7 +3281,7 @@ multiclass avx512_mask_setop { let Predicates = [HasAVX512] in let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1, SchedRW = [WriteZero] in - def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "", + def NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "", [(set KRC:$dst, (VT Val))]>; } @@ -3403,13 +3403,13 @@ multiclass avx512_load opc, string OpcodeStr, string Name, _.ExeDomain>, EVEX, EVEX_KZ, Sched<[Sched.RM]>; } def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)), - (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>; + (!cast(Name#_.ZSuffix#rmkz) _.KRCWM:$mask, addr:$ptr)>; def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)), - (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>; + (!cast(Name#_.ZSuffix#rmkz) _.KRCWM:$mask, addr:$ptr)>; def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))), - (!cast(Name#_.ZSuffix##rmk) _.RC:$src0, + (!cast(Name#_.ZSuffix#rmk) _.RC:$src0, _.KRCWM:$mask, addr:$ptr)>; } @@ -4613,8 +4613,8 @@ multiclass avx512_binop_rmb opc, string OpcodeStr, SDNode OpNode, avx512_binop_rm { defm rmb : AVX512_maskable, AVX512BIBase, EVEX_4V, EVEX_B, @@ -4739,8 +4739,8 @@ multiclass avx512_binop_rm2 opc, string OpcodeStr, defm rmb : AVX512_maskable, AVX512BIBase, EVEX_4V, EVEX_B, @@ -4811,8 +4811,8 @@ multiclass avx512_packs_rmb opc, string OpcodeStr, SDNode OpNode, defm rmb : AVX512_maskable, EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>, @@ -5459,7 +5459,7 @@ multiclass avx512_fp_packed opc, string OpcodeStr, SDPatternOperator OpN let ExeDomain = _.ExeDomain, hasSideEffects = 0, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rr: AVX512_maskable_split opc, string OpcodeStr, SDPatternOperator OpN EVEX_4V, Sched<[sched]>; let mayLoad = 1 in { defm rm: AVX512_maskable_split, EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmb: AVX512_maskable_split, EVEX_4V, EVEX_B, @@ -5489,7 +5489,7 @@ multiclass avx512_fp_round_packed opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain, Uses = [MXCSR] in defm rrb: AVX512_maskable, EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>; @@ -5500,7 +5500,7 @@ multiclass avx512_fp_sae_packed opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain, Uses = [MXCSR] in defm rrb: AVX512_maskable, EVEX_4V, EVEX_B, Sched<[sched]>; @@ -5599,19 +5599,19 @@ multiclass avx512_fp_scalef_p opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rr: AVX512_maskable, EVEX_4V, Sched<[sched]>; defm rm: AVX512_maskable, EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmb: AVX512_maskable, EVEX_4V, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>; } @@ -5621,12 +5621,12 @@ multiclass avx512_fp_scalef_scalar opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rr: AVX512_maskable_scalar, Sched<[sched]>; defm rm: AVX512_maskable_scalar, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -5642,11 +5642,11 @@ multiclass avx512_fp_scalef_all opc, bits<8> opcScaler, string OpcodeStr avx512_fp_round_packed, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; defm SSZ : avx512_fp_scalef_scalar, - avx512_fp_scalar_round, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm SDZ : avx512_fp_scalef_scalar, - avx512_fp_scalar_round, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, VEX_W; @@ -5695,8 +5695,8 @@ multiclass avx512_vptest_mb opc, string OpcodeStr, let ExeDomain = _.ExeDomain, mayLoad = 1, hasSideEffects = 0 in defm rmb : AVX512_maskable_cmp, EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -5784,7 +5784,7 @@ multiclass avx512_shift_rmbi opc, Format ImmFormM, let ExeDomain = _.ExeDomain in defm mbi : AVX512_maskable, EVEX_B, Sched<[sched.Folded]>; } @@ -5967,8 +5967,8 @@ multiclass avx512_var_shift_mb opc, string OpcodeStr, SDNode OpNode, let ExeDomain = _.ExeDomain in defm rmb : AVX512_maskable, AVX5128IBase, EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -6239,8 +6239,8 @@ multiclass avx512_permil_vec OpcVar, string OpcodeStr, SDNode OpNode, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmb: AVX512_maskable, @@ -6522,8 +6522,8 @@ multiclass avx512_fma3p_231_rm opc, string OpcodeStr, SDNode OpNode, defm mb: AVX512_maskable_fma opc, string OpcodeStr, SDNode OpNode, // 213 and 231 patterns this helps tablegen's duplicate pattern detection. defm mb: AVX512_maskable_fma opc, string OpcodeStr, X86SchedWriteWidths sc sched.YMM, "{1to4}", "{y}">, EVEX_V256; } - def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrk") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrkz") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmb") VR128X:$dst, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbk") VR128X:$dst, VK2WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbkz") VR128X:$dst, VK2WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrk") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrkz") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmb") VR128X:$dst, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbk") VR128X:$dst, VK4WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbkz") VR128X:$dst, VK4WM:$mask, f64mem:$src), 0, "att">; @@ -7886,44 +7886,44 @@ multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, MaskOpNode, sched.YMM, "{1to4}", "{y}">, EVEX_V256; } - def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrk") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrkz") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmb") VR128X:$dst, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbk") VR128X:$dst, VK2WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbkz") VR128X:$dst, VK2WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrk") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrkz") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmb") VR128X:$dst, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbk") VR128X:$dst, VK4WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbkz") VR128X:$dst, VK4WM:$mask, f64mem:$src), 0, "att">; @@ -7951,42 +7951,42 @@ multiclass avx512_cvtpd2dq opc, string OpcodeStr, SDNode OpNode, MaskOpNode, sched.YMM, "{1to4}", "{y}">, EVEX_V256; } - def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrk") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrkz") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmb") VR128X:$dst, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbk") VR128X:$dst, VK2WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbkz") VR128X:$dst, VK2WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrk") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrkz") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmb") VR128X:$dst, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbk") VR128X:$dst, VK4WM:$mask, f64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbkz") VR128X:$dst, VK4WM:$mask, f64mem:$src), 0, "att">; @@ -8123,46 +8123,46 @@ multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, NotEVEX2VEXConvertible; } - def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrk") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rrkz") VR128X:$dst, VK2WM:$mask, VR128X:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmb") VR128X:$dst, i64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbk") VR128X:$dst, VK2WM:$mask, i64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z128rmbkz") VR128X:$dst, VK2WM:$mask, i64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrk") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rrkz") VR128X:$dst, VK4WM:$mask, VR256X:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmb") VR128X:$dst, i64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbk") VR128X:$dst, VK4WM:$mask, i64mem:$src), 0, "att">; - def : InstAlias(NAME # "Z256rmbkz") VR128X:$dst, VK4WM:$mask, i64mem:$src), 0, "att">; @@ -8743,7 +8743,7 @@ multiclass avx512_fp14_p opc, string OpcodeStr, SDNode OpNode, Sched<[sched.Folded, sched.ReadAfterFold]>; defm mb: AVX512_maskable, EVEX, T8PD, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -8838,7 +8838,7 @@ multiclass avx512_fp28_p opc, string OpcodeStr, X86VectorVTInfo _, defm mb : AVX512_maskable, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -8920,7 +8920,7 @@ multiclass avx512_sqrt_packed opc, string OpcodeStr, Sched<[sched.Folded, sched.ReadAfterFold]>; defm mb: AVX512_maskable_split, EVEX, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -9069,13 +9069,13 @@ multiclass avx512_rndscale_scalar opc, string OpcodeStr, let Predicates = [HasAVX512] in { def : Pat<(X86any_VRndScale _.FRC:$src1, timm:$src2), - (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + (_.EltVT (!cast(NAME#r) (_.EltVT (IMPLICIT_DEF)), _.FRC:$src1, timm:$src2))>; } let Predicates = [HasAVX512, OptForSize] in { def : Pat<(X86any_VRndScale (_.ScalarLdFrag addr:$src1), timm:$src2), - (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + (_.EltVT (!cast(NAME#m) (_.EltVT (IMPLICIT_DEF)), addr:$src1, timm:$src2))>; } } @@ -9181,12 +9181,12 @@ multiclass avx512_trunc_mr_lowering { def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst), - (!cast(Name#SrcInfo.ZSuffix##mr) + (!cast(Name#SrcInfo.ZSuffix#mr) addr:$dst, SrcInfo.RC:$src)>; def : Pat<(mtruncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst, SrcInfo.KRCWM:$mask), - (!cast(Name#SrcInfo.ZSuffix##mrk) + (!cast(Name#SrcInfo.ZSuffix#mrk) addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>; } @@ -9696,36 +9696,36 @@ multiclass avx512_gather opc, string OpcodeStr, X86VectorVTInfo _, multiclass avx512_gather_q_pd dopc, bits<8> qopc, AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { - defm NAME##D##SUFF##Z: avx512_gather, EVEX_V512, VEX_W; - defm NAME##Q##SUFF##Z: avx512_gather, EVEX_V512, VEX_W; let Predicates = [HasVLX] in { - defm NAME##D##SUFF##Z256: avx512_gather, EVEX_V256, VEX_W; - defm NAME##Q##SUFF##Z256: avx512_gather, EVEX_V256, VEX_W; - defm NAME##D##SUFF##Z128: avx512_gather, EVEX_V128, VEX_W; - defm NAME##Q##SUFF##Z128: avx512_gather, EVEX_V128, VEX_W; } } multiclass avx512_gather_d_ps dopc, bits<8> qopc, AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { - defm NAME##D##SUFF##Z: avx512_gather, + defm NAME#D#SUFF#Z: avx512_gather, EVEX_V512; - defm NAME##Q##SUFF##Z: avx512_gather, + defm NAME#Q#SUFF#Z: avx512_gather, EVEX_V512; let Predicates = [HasVLX] in { - defm NAME##D##SUFF##Z256: avx512_gather, EVEX_V256; - defm NAME##Q##SUFF##Z256: avx512_gather, EVEX_V256; - defm NAME##D##SUFF##Z128: avx512_gather, EVEX_V128; - defm NAME##Q##SUFF##Z128: avx512_gather, EVEX_V128; } } @@ -9753,36 +9753,36 @@ let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain, multiclass avx512_scatter_q_pd dopc, bits<8> qopc, AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { - defm NAME##D##SUFF##Z: avx512_scatter, EVEX_V512, VEX_W; - defm NAME##Q##SUFF##Z: avx512_scatter, EVEX_V512, VEX_W; let Predicates = [HasVLX] in { - defm NAME##D##SUFF##Z256: avx512_scatter, EVEX_V256, VEX_W; - defm NAME##Q##SUFF##Z256: avx512_scatter, EVEX_V256, VEX_W; - defm NAME##D##SUFF##Z128: avx512_scatter, EVEX_V128, VEX_W; - defm NAME##Q##SUFF##Z128: avx512_scatter, EVEX_V128, VEX_W; } } multiclass avx512_scatter_d_ps dopc, bits<8> qopc, AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { - defm NAME##D##SUFF##Z: avx512_scatter, + defm NAME#D#SUFF#Z: avx512_scatter, EVEX_V512; - defm NAME##Q##SUFF##Z: avx512_scatter, + defm NAME#Q#SUFF#Z: avx512_scatter, EVEX_V512; let Predicates = [HasVLX] in { - defm NAME##D##SUFF##Z256: avx512_scatter, EVEX_V256; - defm NAME##Q##SUFF##Z256: avx512_scatter, EVEX_V256; - defm NAME##D##SUFF##Z128: avx512_scatter, EVEX_V128; - defm NAME##Q##SUFF##Z128: avx512_scatter, EVEX_V128; } } @@ -9852,7 +9852,7 @@ defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd multiclass cvt_by_vec_width opc, X86VectorVTInfo Vec, string OpcodeStr > { def rr : AVX512XS8I, EVEX, Sched<[WriteMove]>; // TODO - WriteVecTrunc? } @@ -9963,14 +9963,14 @@ multiclass compress_by_vec_width_common opc, X86VectorVTInfo _, multiclass compress_by_vec_width_lowering { def : Pat<(X86mCompressingStore (_.VT _.RC:$src), addr:$dst, _.KRCWM:$mask), - (!cast(Name#_.ZSuffix##mrk) + (!cast(Name#_.ZSuffix#mrk) addr:$dst, _.KRCWM:$mask, _.RC:$src)>; def : Pat<(X86compress (_.VT _.RC:$src), _.RC:$src0, _.KRCWM:$mask), - (!cast(Name#_.ZSuffix##rrk) + (!cast(Name#_.ZSuffix#rrk) _.RC:$src0, _.KRCWM:$mask, _.RC:$src)>; def : Pat<(X86compress (_.VT _.RC:$src), _.ImmAllZerosV, _.KRCWM:$mask), - (!cast(Name#_.ZSuffix##rrkz) + (!cast(Name#_.ZSuffix#rrkz) _.KRCWM:$mask, _.RC:$src)>; } @@ -10018,23 +10018,23 @@ multiclass expand_by_vec_width opc, X86VectorVTInfo _, multiclass expand_by_vec_width_lowering { def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, undef)), - (!cast(Name#_.ZSuffix##rmkz) + (!cast(Name#_.ZSuffix#rmkz) _.KRCWM:$mask, addr:$src)>; def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, _.ImmAllZerosV)), - (!cast(Name#_.ZSuffix##rmkz) + (!cast(Name#_.ZSuffix#rmkz) _.KRCWM:$mask, addr:$src)>; def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, (_.VT _.RC:$src0))), - (!cast(Name#_.ZSuffix##rmk) + (!cast(Name#_.ZSuffix#rmk) _.RC:$src0, _.KRCWM:$mask, addr:$src)>; def : Pat<(X86expand (_.VT _.RC:$src), _.RC:$src0, _.KRCWM:$mask), - (!cast(Name#_.ZSuffix##rrk) + (!cast(Name#_.ZSuffix#rrk) _.RC:$src0, _.KRCWM:$mask, _.RC:$src)>; def : Pat<(X86expand (_.VT _.RC:$src), _.ImmAllZerosV, _.KRCWM:$mask), - (!cast(Name#_.ZSuffix##rrkz) + (!cast(Name#_.ZSuffix#rrkz) _.KRCWM:$mask, _.RC:$src)>; } @@ -10075,13 +10075,13 @@ multiclass avx512_unary_fp_packed_imm opc, string OpcodeStr, let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rri : AVX512_maskable_split, Sched<[sched]>; defm rmi : AVX512_maskable_split opc, string OpcodeStr, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmbi : AVX512_maskable_split opc, string OpcodeStr, let ExeDomain = _.ExeDomain, Uses = [MXCSR] in defm rrib : AVX512_maskable, @@ -10154,8 +10154,8 @@ multiclass avx512_fp_packed_imm opc, string OpcodeStr, SDNode OpNode, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmbi : AVX512_maskable, EVEX_B, @@ -10197,8 +10197,8 @@ multiclass avx512_3Op_imm8 opc, string OpcodeStr, SDNode OpNode, let ExeDomain = _.ExeDomain in defm rmbi : AVX512_maskable, EVEX_B, @@ -10390,8 +10390,8 @@ multiclass avx512_shuff_packed_128_common opc, string OpcodeStr, EVEX2VEXOverride; defm rmbi : AVX512_maskable opc, string OpcodeStr, defm rmbi : AVX512_maskable, EVEX_B, @@ -10655,8 +10655,8 @@ multiclass avx512_unary_rmb opc, string OpcodeStr, SDNode OpNode, avx512_unary_rm { defm rmb : AVX512_maskable, EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, Sched<[sched.Folded]>; @@ -11175,8 +11175,8 @@ multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmbi : AVX512_maskable_3src opc, string OpcodeStr, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rri : AVX512_maskable_3src, Sched<[sched]>; defm rmi : AVX512_maskable_3src opc, string OpcodeStr, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmbi : AVX512_maskable_3src opc, string OpcodeStr, let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, Uses = [MXCSR] in { defm rrib : AVX512_maskable_3src opc, string OpcodeStr, ExeDomain = _.ExeDomain in { defm rri : AVX512_maskable_3src_scalar opc, string OpcodeStr, let Uses = [MXCSR] in defm rrib : AVX512_maskable_3src_scalar opc, string OpcodeStr, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rmi : AVX512_maskable_3src_scalar Op, string OpStr, string IntPrefix> { loadv2i64, 0, VR128X, i128mem>, EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V128, VEX_WIG; defm Z256 : AESI_binop_rm_int(IntPrefix##"_256"), + !cast(IntPrefix#"_256"), loadv4i64, 0, VR256X, i256mem>, EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V256, VEX_WIG; } let Predicates = [HasAVX512, HasVAES] in defm Z : AESI_binop_rm_int(IntPrefix##"_512"), + !cast(IntPrefix#"_512"), loadv8i64, 0, VR512, i512mem>, EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_WIG; } @@ -11862,8 +11862,8 @@ multiclass VBMI2_shift_var_rmb Op, string OpStr, SDNode OpNode, ExeDomain = VTI.ExeDomain in defm mb: AVX512_maskable_3src, AVX512FMA3Base, EVEX_B, @@ -11897,22 +11897,22 @@ multiclass VBMI2_shift_var_rmb_common Op, string OpStr, SDNode OpNode, } multiclass VBMI2_shift_var wOp, bits<8> dqOp, string Prefix, SDNode OpNode, X86SchedWriteWidths sched> { - defm W : VBMI2_shift_var_rm_common, VEX_W, EVEX_CD8<16, CD8VF>; - defm D : VBMI2_shift_var_rmb_common, EVEX_CD8<32, CD8VF>; - defm Q : VBMI2_shift_var_rmb_common, VEX_W, EVEX_CD8<64, CD8VF>; } multiclass VBMI2_shift_imm wOp, bits<8> dqOp, string Prefix, SDNode OpNode, X86SchedWriteWidths sched> { - defm W : avx512_common_3Op_rm_imm8, VEX_W, EVEX_CD8<16, CD8VF>; - defm D : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; - defm Q : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; } @@ -11960,8 +11960,8 @@ multiclass VNNI_rmb Op, string OpStr, SDNode OpNode, Sched<[sched.Folded, sched.ReadAfterFold]>; defm mb : AVX512_maskable_3src, EVEX_4V, EVEX_CD8<32, CD8VF>, EVEX_B, @@ -12097,8 +12097,8 @@ multiclass GF2P8AFFINE_avx512_rmb_imm Op, string OpStr, SDNode OpNode, let ExeDomain = VTI.ExeDomain in defm rmbi : AVX512_maskable, EVEX_B, @@ -12280,16 +12280,16 @@ multiclass avx512_cvtps2bf16 opc, string OpcodeStr, } // Predicates = [HasBF16, HasVLX] } // ExeDomain = SSEPackedSingle - def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; - def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">; - def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; - def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">; } diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 56bc135d510..9e19a95602d 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3015,28 +3015,28 @@ let Predicates = [HasAVX, NoVLX] in { multiclass sse1_fp_unop_s_intr opc, string OpcodeStr, SDNode OpNode, X86SchedWriteWidths sched, Predicate AVXTarget> { defm SS : sse_fp_unop_s_intr("int_x86_sse_"##OpcodeStr##_ss), + !cast("int_x86_sse_"#OpcodeStr#_ss), UseSSE1, "SS">, XS; defm V#NAME#SS : avx_fp_unop_s_intr("int_x86_sse_"##OpcodeStr##_ss), + !cast("int_x86_sse_"#OpcodeStr#_ss), AVXTarget>, XS, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable; } multiclass sse1_fp_unop_s opc, string OpcodeStr, SDNode OpNode, X86SchedWriteWidths sched, Predicate AVXTarget> { - defm SS : sse_fp_unop_s, XS; - defm V#NAME#SS : avx_fp_unop_s, XS, VEX_4V, VEX_LIG, VEX_WIG; } multiclass sse2_fp_unop_s opc, string OpcodeStr, SDNode OpNode, X86SchedWriteWidths sched, Predicate AVXTarget> { - defm SD : sse_fp_unop_s, XD; - defm V#NAME#SD : avx_fp_unop_s, XD, VEX_4V, VEX_LIG, VEX_WIG; } @@ -6725,7 +6725,7 @@ multiclass AESI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, PatFrag ld_frag, bit Is2Addr = 0, RegisterClass RC = VR128, X86MemOperand MemOp = i128mem> { - let AsmString = OpcodeStr## + let AsmString = OpcodeStr# !if(Is2Addr, "\t{$src2, $dst|$dst, $src2}", "\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { def rr : AES8I { - def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", (!cast(InstStr # "rr") RC:$dst, RC:$src1, RC:$src2, !add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>; - def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", (!cast(InstStr # "rm") RC:$dst, RC:$src1, MemOp:$src2, !add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>; } @@ -7935,8 +7935,8 @@ multiclass GF2P8MULB_rm { let ExeDomain = SSEPackedInt, AsmString = !if(Is2Addr, - OpcodeStr##"\t{$src2, $dst|$dst, $src2}", - OpcodeStr##"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { + OpcodeStr#"\t{$src2, $dst|$dst, $src2}", + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { let isCommutable = 1 in def rr : PDI<0xCF, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), "", [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, RC:$src2)))]>, @@ -7953,8 +7953,8 @@ multiclass GF2P8AFFINE_rmi Op, string OpStr, ValueType OpVT, SDNode OpNode, RegisterClass RC, PatFrag MemOpFrag, X86MemOperand X86MemOp, bit Is2Addr = 0> { let AsmString = !if(Is2Addr, - OpStr##"\t{$src3, $src2, $dst|$dst, $src2, $src3}", - OpStr##"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}") in { + OpStr#"\t{$src3, $src2, $dst|$dst, $src2, $src3}", + OpStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}") in { def rri : Ii8 Op, string OpStr, SDNode OpNode> { defm NAME : GF2P8AFFINE_rmi; let Predicates = [HasGFNI, HasAVX, NoVLX_Or_NoBWI] in { - defm V##NAME : GF2P8AFFINE_rmi, VEX_4V, VEX_W; - defm V##NAME##Y : GF2P8AFFINE_rmi, VEX_4V, VEX_L, VEX_W; } }