From d1a0918ad205c1d4360fce449b7d4573e159765b Mon Sep 17 00:00:00 2001
From: Saleem Abdulrasool <compnerd@compnerd.org>
Date: Fri, 22 Sep 2017 04:31:44 +0000
Subject: [PATCH] AArch64: support SwiftCC properly on AAPCS64

The previous SwiftCC support for AAPCS64 was partially correct.  It
setup swiftself parameters in the proper register but failed to setup
swifterror in the correct register.  This would break compilation of
swift code for non-Darwin AAPCS64 conforming environments.

llvm-svn: 313956
---
 lib/Target/AArch64/AArch64CallingConvention.td |  3 +++
 test/CodeGen/AArch64/swift-error.ll            | 18 ++++++++++++++++++
 2 files changed, 21 insertions(+)
 create mode 100644 test/CodeGen/AArch64/swift-error.ll

diff --git a/lib/Target/AArch64/AArch64CallingConvention.td b/lib/Target/AArch64/AArch64CallingConvention.td
index 291bc5ea858..93a68449de8 100644
--- a/lib/Target/AArch64/AArch64CallingConvention.td
+++ b/lib/Target/AArch64/AArch64CallingConvention.td
@@ -49,6 +49,9 @@ def CC_AArch64_AAPCS : CallingConv<[
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>,
 
+  // A SwiftError is passed in X21.
+  CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
+
   CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
 
   // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
diff --git a/test/CodeGen/AArch64/swift-error.ll b/test/CodeGen/AArch64/swift-error.ll
new file mode 100644
index 00000000000..79a31c19be1
--- /dev/null
+++ b/test/CodeGen/AArch64/swift-error.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple aarch64-unknown-linux-gnu -filetype asm -o - %s | FileCheck %s
+
+%swift.error = type opaque
+
+declare swiftcc void @f(%swift.error** swifterror)
+
+define swiftcc void @g(i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %swift.error** swifterror %error) {
+entry:
+  call swiftcc void @f(%swift.error** nonnull nocapture swifterror %error)
+  ret void
+}
+
+; CHEECK-LABEL: g
+; CHECK: str x30, [sp, #-16]!
+; CHECK: bl f
+; CHECK: ldr x30, [sp], #16
+; CHECK: ret
+