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[MachineLICM] delete dead flag if the duplicated def outside of loop is dead.
Fixup dead flags for CSE-ed instructions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D92557
This commit is contained in:
Chen Zheng
parent
5479e7404d
commit
d1ab1dfd14
@ -157,7 +157,7 @@ namespace {
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SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
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// For each opcode, keep a list of potential CSE instructions.
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DenseMap<unsigned, std::vector<const MachineInstr *>> CSEMap;
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DenseMap<unsigned, std::vector<MachineInstr *>> CSEMap;
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enum {
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SpeculateFalse = 0,
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@ -259,13 +259,12 @@ namespace {
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MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
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const MachineInstr *
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LookForDuplicate(const MachineInstr *MI,
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std::vector<const MachineInstr *> &PrevMIs);
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MachineInstr *LookForDuplicate(const MachineInstr *MI,
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std::vector<MachineInstr *> &PrevMIs);
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bool EliminateCSE(
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MachineInstr *MI,
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DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI);
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bool
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EliminateCSE(MachineInstr *MI,
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DenseMap<unsigned, std::vector<MachineInstr *>>::iterator &CI);
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bool MayCSE(MachineInstr *MI);
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@ -1405,10 +1404,10 @@ void MachineLICMBase::InitCSEMap(MachineBasicBlock *BB) {
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/// Find an instruction amount PrevMIs that is a duplicate of MI.
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/// Return this instruction if it's found.
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const MachineInstr*
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MachineInstr *
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MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
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std::vector<const MachineInstr*> &PrevMIs) {
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for (const MachineInstr *PrevMI : PrevMIs)
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std::vector<MachineInstr *> &PrevMIs) {
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for (MachineInstr *PrevMI : PrevMIs)
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if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
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return PrevMI;
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@ -1419,14 +1418,15 @@ MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
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/// computes the same value. If it's found, do a RAU on with the definition of
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/// the existing instruction rather than hoisting the instruction to the
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/// preheader.
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bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
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DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI) {
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bool MachineLICMBase::EliminateCSE(
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MachineInstr *MI,
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DenseMap<unsigned, std::vector<MachineInstr *>>::iterator &CI) {
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// Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
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// the undef property onto uses.
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if (CI == CSEMap.end() || MI->isImplicitDef())
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return false;
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if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
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if (MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
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LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
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// Replace virtual registers defined by MI by their counterparts defined
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@ -1466,6 +1466,9 @@ bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
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Register DupReg = Dup->getOperand(Idx).getReg();
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MRI->replaceRegWith(Reg, DupReg);
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MRI->clearKillFlags(DupReg);
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// Clear Dup dead flag if any, we reuse it for Reg.
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if (!MRI->use_nodbg_empty(DupReg))
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Dup->getOperand(Idx).setIsDead(false);
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}
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MI->eraseFromParent();
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@ -1479,8 +1482,8 @@ bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
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/// the loop.
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bool MachineLICMBase::MayCSE(MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator
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CI = CSEMap.find(Opcode);
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DenseMap<unsigned, std::vector<MachineInstr *>>::iterator CI =
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CSEMap.find(Opcode);
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// Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
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// the undef property onto uses.
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if (CI == CSEMap.end() || MI->isImplicitDef())
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@ -1534,8 +1537,8 @@ bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
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// Look for opportunity to CSE the hoisted instruction.
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unsigned Opcode = MI->getOpcode();
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DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator
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CI = CSEMap.find(Opcode);
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DenseMap<unsigned, std::vector<MachineInstr *>>::iterator CI =
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CSEMap.find(Opcode);
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if (!EliminateCSE(MI, CI)) {
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// Otherwise, splice the instruction to the preheader.
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Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
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84
test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
Normal file
84
test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
Normal file
@ -0,0 +1,84 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: deadFlagAfterCSE
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# This case tests that after the dead %3 is CSE-ed with hoisted %5 in MachineLICM
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# pass, the dead flag will be cleared for %3 if %5 has users.
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: deadFlagAfterCSE
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $x3, $x4
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; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
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; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x4
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; CHECK: [[ADD8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADD8 [[COPY]], [[COPY1]]
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; CHECK: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[ADD8_]], 100
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[PHI:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADD8_]], %bb.0, %5, %bb.1
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; CHECK: STDX [[PHI]], [[ADDI8_]], [[ADD8_]]
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; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = nuw ADDI8 [[PHI]], 1
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; CHECK: B %bb.1
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; CHECK: bb.2:
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; CHECK: BLR8 implicit $lr8, implicit $rm
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bb.0:
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liveins: $x3, $x4
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%0:g8rc = COPY $x3
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%1:g8rc = COPY $x4
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%2:g8rc_and_g8rc_nox0 = ADD8 %0, %1
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dead %3:g8rc_and_g8rc_nox0 = ADDI8 %2, 100
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B %bb.1
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bb.1:
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%4:g8rc_and_g8rc_nox0 = PHI %2, %bb.0, %6, %bb.1
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%5:g8rc_and_g8rc_nox0 = ADDI8 %2, 100
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STDX %4, %5, %2
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%6:g8rc = nuw ADDI8 %4, 1
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B %bb.1
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bb.2:
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: deadFlagAfterCSE2
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# This case tests that after the dead %3 is CSE-ed with hoisted dead %5 in
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# MachineLICM pass, the dead flag will be kept.
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: deadFlagAfterCSE2
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $x3, $x4
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; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
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; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x4
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; CHECK: [[ADD8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADD8 [[COPY]], [[COPY1]]
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; CHECK: dead %3:g8rc_and_g8rc_nox0 = ADDI8 [[ADD8_]], 100
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[PHI:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADD8_]], %bb.0, %5, %bb.1
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; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = nuw ADDI8 [[PHI]], 1
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; CHECK: B %bb.1
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; CHECK: bb.2:
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; CHECK: BLR8 implicit $lr8, implicit $rm
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bb.0:
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liveins: $x3, $x4
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%0:g8rc = COPY $x3
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%1:g8rc = COPY $x4
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%2:g8rc_and_g8rc_nox0 = ADD8 %0, %1
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dead %3:g8rc_and_g8rc_nox0 = ADDI8 %2, 100
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B %bb.1
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bb.1:
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%4:g8rc_and_g8rc_nox0 = PHI %2, %bb.0, %6, %bb.1
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dead %5:g8rc_and_g8rc_nox0 = ADDI8 %2, 100
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%6:g8rc = nuw ADDI8 %4, 1
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B %bb.1
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bb.2:
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BLR8 implicit $lr8, implicit $rm
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...
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