From d1c9440bfafd24a2dbbeb7d20616c16679a9da7d Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <Valery.Pykhtin@amd.com>
Date: Tue, 1 Nov 2016 10:26:48 +0000
Subject: [PATCH] [AMDGPU] Expand vector mulhu/mulhs

Differential revision: https://reviews.llvm.org/D26077

llvm-svn: 285684
---
 lib/Target/AMDGPU/AMDGPUISelLowering.cpp |  2 ++
 test/CodeGen/AMDGPU/sdiv.ll              | 13 +++++++++++++
 test/CodeGen/AMDGPU/udiv.ll              | 13 +++++++++++++
 3 files changed, 28 insertions(+)

diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index a7fd748e85d..a69d1afdea8 100644
--- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -359,6 +359,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FP_TO_SINT, VT, Expand);
     setOperationAction(ISD::FP_TO_UINT, VT, Expand);
     setOperationAction(ISD::MUL,  VT, Expand);
+    setOperationAction(ISD::MULHU, VT, Expand);
+    setOperationAction(ISD::MULHS, VT, Expand);
     setOperationAction(ISD::OR,   VT, Expand);
     setOperationAction(ISD::SHL,  VT, Expand);
     setOperationAction(ISD::SRA,  VT, Expand);
diff --git a/test/CodeGen/AMDGPU/sdiv.ll b/test/CodeGen/AMDGPU/sdiv.ll
index 29d893414c0..66caad4677b 100644
--- a/test/CodeGen/AMDGPU/sdiv.ll
+++ b/test/CodeGen/AMDGPU/sdiv.ll
@@ -156,3 +156,16 @@ define void @v_sdiv_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) {
 ;   store i64 %result, i64 addrspace(1)* %out, align 8
 ;   ret void
 ; }
+
+; FUNC-LABEL: @scalarize_mulhs_4xi32
+; SI: v_mul_hi_i32
+; SI: v_mul_hi_i32
+; SI: v_mul_hi_i32
+; SI: v_mul_hi_i32
+
+define void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
+  %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
+  %2 = sdiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
+  store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
+  ret void
+}
diff --git a/test/CodeGen/AMDGPU/udiv.ll b/test/CodeGen/AMDGPU/udiv.ll
index f72c22095e4..02383a97205 100644
--- a/test/CodeGen/AMDGPU/udiv.ll
+++ b/test/CodeGen/AMDGPU/udiv.ll
@@ -145,3 +145,16 @@ define void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
   store i32 %result.ext, i32 addrspace(1)* %out
   ret void
 }
+
+; FUNC-LABEL: @scalarize_mulhu_4xi32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+
+define void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
+  %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
+  %2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
+  store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
+  ret void
+}